Patents by Inventor Hao-Ming Lien
Hao-Ming Lien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8895446Abstract: A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.Type: GrantFiled: February 18, 2013Date of Patent: November 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Tang Peng, Tai-Chun Huang, Hao-Ming Lien
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Publication number: 20140264491Abstract: An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip.Type: ApplicationFiled: April 19, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tai-Chun Huang, Chih-Tang Peng, Chia-Wei Chang, Ming-Hua Yu, Hao-Ming Lien, Chao-Cheng Chen, Tze-Liang Lee
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Publication number: 20140252497Abstract: An isolation region gap fill method comprises depositing a first dielectric material over a semiconductor device through a flowable deposition process or other gap fill deposition processes, wherein the semiconductor device includes a first FinFET comprising a plurality of first fins and a second FinFET comprising a plurality of second fins. The method further comprises removing the first dielectric material between the first FinFET and the second FinFET to form an inter-device gap, depositing a second dielectric material into the inter-device gap and applying an annealing process to the semiconductor device.Type: ApplicationFiled: March 8, 2013Publication date: September 11, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Tang Peng, Tai-Chung Huang, Hao-Ming Lien, Tze-Liang Lee
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Patent number: 8828841Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.Type: GrantFiled: January 13, 2014Date of Patent: September 9, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Tang Peng, Bing-Hung Chen, Tze-Liang Lee, Hao-Ming Lien
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Publication number: 20140242776Abstract: A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.Type: ApplicationFiled: April 22, 2014Publication date: August 28, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mong-Song Liang, Tze-Liang Lee, Kuo-Tai Huang, Chao-Cheng Chen, Hao-Ming Lien, Chih-Tang Peng
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Publication number: 20140231919Abstract: A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.Type: ApplicationFiled: February 18, 2013Publication date: August 21, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Tang Peng, Tai-Chun Huang, Hao-Ming Lien
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Patent number: 8735252Abstract: A method of fabricating a semiconductor IC is disclosed. The method includes receiving a device. The device includes a semiconductor substrate, a plurality of fins and trenches between fins in the semiconductor substrate. The method also includes filling the trenches with a dielectric material to form shallow trench isolations (STI), applying a low-thermal-budget annealing to the dielectric material, and applying a wet-treatment to the dielectric material.Type: GrantFiled: June 7, 2012Date of Patent: May 27, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Weibo Yu, Ming-Hsi Yeh, Chih-Tang Peng, Hao-Ming Lien, Chao-Cheng Chen, Syun-Ming Jang
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Patent number: 8736016Abstract: An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.Type: GrantFiled: June 7, 2007Date of Patent: May 27, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mong-Song Liang, Tze-Liang Lee, Kuo-Tai Huang, Chao-Cheng Chen, Hao-Ming Lien, Chih-Tang Peng
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Publication number: 20140127879Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgas sing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.Type: ApplicationFiled: January 13, 2014Publication date: May 8, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Tang Peng, Bing-Hung Chen, Tze-Liang Lee, Hao-Ming Lien
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Patent number: 8629508Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.Type: GrantFiled: December 11, 2012Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Tang Peng, Bing-Hung Chen, Tze-Liang Lee, Hao-Ming Lien
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Publication number: 20130330906Abstract: A method of fabricating a semiconductor IC is disclosed. The method includes receiving a device. The device includes a semiconductor substrate, a plurality of fins and trenches between fins in the semiconductor substrate. The method also includes filling the trenches with a dielectric material to form shallow trench isolations (STI), applying a low-thermal-budget annealing to the dielectric material, and applying a wet-treatment to the dielectric material.Type: ApplicationFiled: June 7, 2012Publication date: December 12, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Weibo Yu, Ming-His Yeh, Chih-Tang Peng, Hao-Ming Lien, Chao-Cheng Chen, Syun-Ming Jang
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Patent number: 8580653Abstract: A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide.Type: GrantFiled: February 25, 2013Date of Patent: November 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tze-Liang Lee, Pei-Ren Jeng, Chu-Yun Fu, Chyi Shyuan Chern, Jui-Hei Huang, Chih-Tang Peng, Hao-Ming Lien
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Publication number: 20130277760Abstract: A FinFET device may include a dummy FinFET structure laterally adjacent an active FinFET structure to reduce stress imbalance and the effects of stress imbalance on the active FinFET structure. The FinFET device comprises an active FinFET comprising a plurality of semiconductor fins, and a dummy FinFET comprising a plurality of semiconductor fins. The active FinFET and the dummy FinFET are laterally spaced from each other by a spacing that is related to the fin pitch of the active FinFET.Type: ApplicationFiled: April 24, 2012Publication date: October 24, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chang-Shen Lu, Chih-Tang Peng, Tai-Chun Huang, Pei-Ren Jeng, Hao-Ming Lien, Yi-Hung Lin, Tze-Liang Lee, Syun-Ming Jang
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Publication number: 20130171803Abstract: A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide.Type: ApplicationFiled: February 25, 2013Publication date: July 4, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tze-Liang LEE, Pei-Ren JENG, Chu-Yun FU, Chyi Shyuan CHERN, Jui-Hei HUANG, Chih-Tang PENG, Hao-Ming LIEN
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Publication number: 20130137251Abstract: A method includes performing a plasma treatment on a first surface of a first material and a second surface of a second material simultaneously, wherein the first material is different from the second material. A third material is formed on treated first surface of the first material and on treated second surface of the second material. The first, the second, and the third materials may include a hard mask, a semiconductor material, and an oxide, respectively.Type: ApplicationFiled: November 30, 2011Publication date: May 30, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ling Liou, Chih-Tang Peng, Pei-Ren Jeng, Hao-Ming Lien, Tze-Liang Lee
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Patent number: 8450161Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.Type: GrantFiled: May 7, 2012Date of Patent: May 28, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hao Chen, Hao-Ming Lien, Ssu-Yu Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang
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Patent number: 8404561Abstract: The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide; exposing a surface of the first silicon oxide to a vapor mixture comprising NH3 and a fluorine-containing compound; heating the substrate to a temperature between 100° C. to 200° C.; and filling the trench with a second silicon oxide, whereby the isolation structure made has almost no void.Type: GrantFiled: May 5, 2010Date of Patent: March 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tze-Liang Lee, Pei-Ren Jeng, Chu-Yun Fu, Chyi Shyuan Chern, Jui-Hei Huang, Chih-Tang Peng, Hao-Ming Lien
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Patent number: 8329552Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.Type: GrantFiled: July 22, 2011Date of Patent: December 11, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Tang Peng, Bing-Hung Chen, Tze-Liang Lee, Hao-Ming Lien
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Publication number: 20120225529Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.Type: ApplicationFiled: May 7, 2012Publication date: September 6, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chieh-Hao Chen, Hao-Ming Lien, Ssu-Yu Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang
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Patent number: 8193586Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.Type: GrantFiled: February 20, 2009Date of Patent: June 5, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hao Chen, Hao-Ming Lien, Ssu-Yi Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang, Chien-Liang Chen