Patents by Inventor Hao-Tian Zhu

Hao-Tian Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10923790
    Abstract: Systems and methods which provide low-loss dielectric microstrip line (DML) circuits for use with respect to signals in the terahertz frequency range are described. Low-loss DML integrated circuits of embodiments, such as may comprise DML transmission lines, DML couplers, DML crossovers, etc., may be based on silicon technology and are adapted for signal frequencies in the range of 750-925 GHz. A DML circuit implementation may be comprised of silicon on insulator based DML structure having a silicon dioxide (SiO2) insulation layer as the middle layer of the DML, wherein the device layer (HR—Si) and the handle layer (HR—Si) are the top and bottom layers of the DML. A high-precision fabrication process for the SOI wafer, wherein the height of the dielectric microstrip lines can be accurately controlled, may be utilized to fabricate DML circuits of embodiments. A non-contact measurement technology may be used to test the DML circuits of embodiments.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: February 16, 2021
    Assignee: City University of Hong Kong
    Inventors: Quan Xue, Hao-Tian Zhu
  • Publication number: 20180241128
    Abstract: Systems and methods which provide low-loss dielectric microstrip line (DML) circuits for use with respect to signals in the terahertz frequency range are described. Low-loss DML integrated circuits of embodiments, such as may comprise DML transmission lines, DML couplers, DML crossovers, etc., may be based on silicon technology and are adapted for signal frequencies in the range of 750-925 GHz. A DML circuit implementation may he comprised of silicon on insulator based DML structure having a silicon dioxide (SiO2) insulation layer as the middle layer of the DML, wherein the device layer (HR—Si) and the handle layer (HR—Si) are the top and bottom layers of the DML. A high-precision fabrication process for the SOI wafer, wherein the height of the dielectric microstrip lines can be accurately controlled, may be utilized to fabricate DML circuits of embodiments. A non-contact measurement technology may be used to test the DML circuits of embodiments.
    Type: Application
    Filed: February 20, 2017
    Publication date: August 23, 2018
    Inventors: Quan Wue, Hao-Tian Zhu