Patents by Inventor Hardik K. Doshi

Hardik K. Doshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200356417
    Abstract: A method and apparatus of a device that load balances a first plurality of Peripheral Connect Interconnect ports is described. In an exemplary embodiment, the device detects a second plurality of PCI ports in the device. In addition, the device determines a load for each port in the first and second plurality of PCI ports and sorts the second plurality of PCI ports. The device further load balances the first plurality of PCI ports using at least a PCIe switch and the load determination of the second plurality of PCI ports. The device additionally communicates data between the first and second plurality of PCI ports.
    Type: Application
    Filed: May 12, 2020
    Publication date: November 12, 2020
    Inventors: Michael W. MURPHY, Gopal Thirumalai NARAYANAN, Deepak K. MISHRA, Andre M. GLOVER, Sreenivas TALLAM, Hardik K. DOSHI
  • Patent number: 10795427
    Abstract: A method from managing power state transitions in a computing system is disclosed. A processor may initiate a change in power state from a first initial power state to a first new power state and, in response to initiating the change, send an initial notification to a system integrated circuit using a first communication channel, and deactivate the first communication based on responses to the initial notification. The processor may enter the first new power state in response to the deactivation of the first communication channel, and send a final notification to a management controller using a second communication channel. The management controller may send a message to the system integrated circuit upon receiving the final notification. The system integrated circuit may then transition from a second initial power state to a second new power state based on the message.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 6, 2020
    Assignee: Apple Inc.
    Inventors: Hardik K. Doshi, Gopal Thirumalai Narayanan, Siddharth P. Shah, Joseph J. Castro, Craig S. Forbell, Christopher M. Aycock, Varaprasad V. Lingutla
  • Patent number: 10417429
    Abstract: A method and apparatus for protecting boot variables is disclosed. A computer system includes a main processor and an auxiliary processor. The auxiliary processor includes a non-volatile memory that stores variables associated with boot code that is also stored thereon. The main processor may send a request to the auxiliary processor to alter one of the variables stored in the non-volatile memory. Responsive to receiving the request, the auxiliary processor may execute a security policy to determine if the main processor meets the criteria for altering the variable. If the auxiliary processor determines that the main processor meets the criteria, it may grant permission to alter the variable.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 17, 2019
    Assignee: Apple Inc.
    Inventors: Joshua P. de Cesare, Timothy R. Paaske, Xeno S. Kovah, Nikolaj Schlej, Jeffrey R. Wilcox, Hardik K. Doshi, Kevin H. Alderfer, Corey T. Kallenberg
  • Publication number: 20190250925
    Abstract: A computing device may comprise a first processor and a secondary processor. The first processor may initiate a power management process transitioning the first processor from a first state to a second state and, upon reaching a predetermined step in the power management process, notify the secondary processor of the power management process. The secondary processor may initiate, in response to the notifying, a parallel power management process transitioning the secondary processor from an equivalent first state to an equivalent second state.
    Type: Application
    Filed: March 1, 2019
    Publication date: August 15, 2019
    Applicant: Apple Inc.
    Inventor: Hardik K. Doshi
  • Publication number: 20190179695
    Abstract: One embodiment provides for a data processing system comprising multiple independent processors to execute multiple operating system environments of the data processing system, the multiple operating system environments to enable operation of multiple regions of a computing device associated with the data processing system. The multiple operating system environments are interconnected via a transport agnostic communication link. In response to detection of a fatal error in one or more of the multiple operating system environments, the multiple operating system environments coordinate performance of multiple separate error handling operations within the multiple operating system environments to generate a combined error log. The combined error log includes operational states of the multiple operating system environments.
    Type: Application
    Filed: September 28, 2018
    Publication date: June 13, 2019
    Inventors: Christopher J. Noe, Joshua H. Berlin, Joseph J. Castro, Hardik K. Doshi, Joel N. Kerr, Kerry J. Kopp, Michael J. Smith
  • Publication number: 20190114433
    Abstract: A method and apparatus for protecting boot variables is disclosed. A computer system includes a main processor and an auxiliary processor. The auxiliary processor is associated with a non-volatile memory that stores variables associated with boot code that is also stored thereon. The main processor may send a request to the auxiliary processor to alter one of the variables stored in the non-volatile memory. Responsive to receiving the request, the auxiliary processor may execute a security policy to determine if the main processor meets the criteria for altering the variable. If the auxiliary processor determines that the main processor meets the criteria, it may grant permission to alter the variable.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 18, 2019
    Inventors: Joshua P. de Cesare, Timothy R. Paaske, Xeno S. Kovah, Nikolaj Schlej, Jeffrey R. Wilcox, Hardik K. Doshi, Kevin H. Alderfer, Corey T. Kallenberg
  • Publication number: 20190102558
    Abstract: A method and apparatus for performing a secure boot of a computer system is disclosed. A computer system according to the disclosure includes an auxiliary processor and a main processor. The boot process includes initially booting the auxiliary processor. The auxiliary processor is associated with a non-volatile memory storing boot code for the main processor. The auxiliary processor may perform a verification of the boot code. Subsequent to verifying the boot code, the main processor may be released from a reset state. Once the main processor is no longer in the reset state, the boot code may be provided thereto. Thereafter, the boot procedure may continue with the main processor executing the boot code.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 4, 2019
    Inventors: Joshua P. de Cesare, Timothy R. Paaske, Xeno S. Kovah, Nikolaj Schlej, Jeffrey R. Wilcox, Ezekiel T. Runyon, Hardik K. Doshi, Kevin H. Alderfer, Corey T. Kallenberg
  • Patent number: 10223128
    Abstract: A computing device may comprise a first processor and a secondary processor. The first processor may initiate a power management process transitioning the first processor from a first state to a second state and, upon reaching a predetermined step in the power management process, notify the secondary processor of the power management process. The secondary processor may initiate, in response to the notifying, a parallel power management process transitioning the secondary processor from an equivalent first state to an equivalent second state.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: March 5, 2019
    Assignee: Apple Inc.
    Inventor: Hardik K. Doshi
  • Publication number: 20180349609
    Abstract: A method and apparatus for protecting boot variables is disclosed. A computer system includes a main processor and an auxiliary processor. The auxiliary processor includes a non-volatile memory that stores variables associated with boot code that is also stored thereon. The main processor may send a request to the auxiliary processor to alter one of the variables stored in the non-volatile memory. Responsive to receiving the request, the auxiliary processor may execute a security policy to determine if the main processor meets the criteria for altering the variable. If the auxiliary processor determines that the main processor meets the criteria, it may grant permission to alter the variable.
    Type: Application
    Filed: September 29, 2017
    Publication date: December 6, 2018
    Inventors: Joshua P. de Cesare, Timothy R. Paaske, Xeno S. Kovah, Nikolaj Schlej, Jeffrey R. Wilcox, Hardik K. Doshi, Kevin H. Alderfer, Corey T. Kallenberg
  • Publication number: 20180348850
    Abstract: A method from managing power state transitions in a computing system is disclosed. A processor may initiate a change in power state from a first initial power state to a first new power state and, in response to initiating the change, send an initial notification to a system integrated circuit using a first communication channel, and deactivate the first communication based on responses to the initial notification. The processor may enter the first new power state in response to the deactivation of the first communication channel, and send a final notification to a management controller using a second communication channel. The management controller may send a message to the system integrated circuit upon receiving the final notification. The system integrated circuit may then transition from a second initial power state to a second new power state based on the message.
    Type: Application
    Filed: September 29, 2017
    Publication date: December 6, 2018
    Inventors: Hardik K. Doshi, Gopal Thirumalai Narayanan, Siddharth P. Shah, Joseph J. Castro, Craig S. Forbell, Christopher M. Aycock, Varaprasad V. Lingutla
  • Publication number: 20180349608
    Abstract: A method and apparatus for performing a secure boot of a computer system is disclosed. A computer system according to the disclosure includes an auxiliary processor and a main processor. The boot process includes initially booting the auxiliary processor. The auxiliary processor includes a non-volatile memory storing boot code for the main processor. The auxiliary processor may perform a verification of the boot code. Subsequent to verifying the boot code, the main processor may be released from a reset state. Once the main processor is no longer in the reset state, the boot code may be provided thereto. Thereafter, the boot procedure may continue with the main processor executing the boot code.
    Type: Application
    Filed: September 29, 2017
    Publication date: December 6, 2018
    Inventors: Joshua P. de Cesare, Timothy R. Paaske, Xeno S. Kovah, Nikolaj Schlej, Jeffrey R. Wilcox, Ezekiel T. Runyon, Hardik K. Doshi, Kevin H. Alderfer, Corey T. Kallenberg
  • Publication number: 20180088961
    Abstract: A computing device may comprise a first processor and a secondary processor. The first processor may initiate a power management process transitioning the first processor from a first state to a second state and, upon reaching a predetermined step in the power management process, notify the secondary processor of the power management process. The secondary processor may initiate, in response to the notifying, a parallel power management process transitioning the secondary processor from an equivalent first state to an equivalent second state.
    Type: Application
    Filed: October 4, 2016
    Publication date: March 29, 2018
    Applicant: Apple Inc.
    Inventor: Hardik K. Doshi