Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.

Abstract: Embodiments described herein provide regression testing using artificial intelligence. A regression testing network model for a first plurality of organizations using a common codebase is provided. The regression testing network model provides an organization finite state machine (FSM) model for each organization. A first dataset including samples of the organization FSM models based on regression testing for one or more previous releases of the common codebase prior to a first release of the common codebase is received. A training dataset is generated based on the first dataset. The regression testing network model using the training dataset. A second plurality of organizations for regression testing for the first release is determined, from the first plurality of organizations, using the trained regression testing network model.

Abstract: The disclosure relates to a latch including a first inverter with a first pair of field effect transistors (FETs) configured with a first channel width to length ratio (W/L), and a second inverter with a second pair of FETs configured with a second W/L different than the first W/L. Another latch includes first and second inverters; a first negative feedback circuit including first and second FETs coupled between first and second voltage rails, the input of the first inverter coupled between the first and second FETs, and the first and second FETs including gates coupled to an output of the first inverter; and a second negative feedback circuit including third and fourth FETs coupled between the first and second voltage rails, the input of the second inverter coupled between the third and fourth FETs, and the third and fourth FETs including gates coupled to an output of the second inverter.

Abstract: The disclosure relates to a latch including a first inverter with a first pair of field effect transistors (FETs) configured with a first channel width to length ratio (W/L), and a second inverter with a second pair of FETs configured with a second W/L different than the first W/L. Another latch includes first and second inverters; a first negative feedback circuit including first and second FETs coupled between first and second voltage rails, the input of the first inverter coupled between the first and second FETs, and the first and second FETs including gates coupled to an output of the first inverter; and a second negative feedback circuit including third and fourth FETs coupled between the first and second voltage rails, the input of the second inverter coupled between the third and fourth FETs, and the third and fourth FETs including gates coupled to an output of the second inverter.

Abstract: A triple modular redundancy (TMR) flip-flop includes a set of master-gate-latch circuits including a first set of inputs to receive a first digital signal, and a second set of inputs to receive a clock; and a voting logic circuit including a set of inputs coupled to a set of outputs of the set of master-gate-latch circuits, and an output to generate a second digital signal based on the first digital signal. Another TMR flip-flop includes a set of master-gate-latch circuits to receive a set of digital signals in response to a first edge of a clock, respectively; and latch the set of digital signals in response to a second edge of the clock, respectively; and a voting logic circuit to receive the latched set of digital signals; and generate a second digital signal based on a majority of logic levels of the latched first set of digital signals, respectively.

Abstract: A triple modular redundancy (TMR) flip-flop includes a set of master-gate-latch circuits including a first set of inputs to receive a first digital signal, and a second set of inputs to receive a clock; and a voting logic circuit including a set of inputs coupled to a set of outputs of the set of master-gate-latch circuits, and an output to generate a second digital signal based on the first digital signal. Another TMR flip-flop includes a set of master-gate-latch circuits to receive a set of digital signals in response to a first edge of a clock, respectively; and latch the set of digital signals in response to a second edge of the clock, respectively; and a voting logic circuit to receive the latched set of digital signals; and generate a second digital signal based on a majority of logic levels of the latched first set of digital signals, respectively.

Abstract: Certain aspects of the present disclosure provide apparatus and methods for performing memory read operations. One example method generally includes precharging a plurality of memory columns during a precharging phase of a read access cycle. The method also includes sensing first data stored in a first memory cell of a first memory column of the plurality of memory columns during a memory read phase of the read access cycle, and sensing second data stored in a second memory cell of a second memory column of the plurality of memory columns during the same memory read phase of the read access cycle.

Abstract: Certain aspects of the present disclosure provide apparatus and methods for performing memory read operations. One example method generally includes precharging a plurality of memory columns during a precharging phase of a read access cycle. The method also includes sensing first data stored in a first memory cell of a first memory column of the plurality of memory columns during a memory read phase of the read access cycle, and sensing second data stored in a second memory cell of a second memory column of the plurality of memory columns during the same memory read phase of the read access cycle.

Abstract: A multi-bit adder apparatus comprising: a full adder stage configured to receive at least some of a plurality of least significant bits (LSBs) of first data and second data; and a half adder stage configured to receive at least some of a plurality of most significant bits (MSBs) of the first data and the second data; a carry generation stage coupled to the full adder stage and the half adder stage, wherein the carry generation stage includes at least one serial propagate-generate (PG) component; and a post summing stage coupled to the carry generation stage and the half adder stage and configured to generate a partial sum output of the first data and the second data, wherein a number of the at least some of the plurality of LSBs is different from a number of the at least some of the plurality of MSBs.

Abstract: A multi-bit adder apparatus comprising: a full adder stage configured to receive at least some of a plurality of least significant bits (LSBs) of first data and second data; and a half adder stage configured to receive at least some of a plurality of most significant bits (MSBs) of the first data and the second data; a carry generation stage coupled to the full adder stage and the half adder stage, wherein the carry generation stage includes at least one serial propagate-generate (PG) component; and a post summing stage coupled to the carry generation stage and the half adder stage and configured to generate a partial sum output of the first data and the second data, wherein a number of the at least some of the plurality of LSBs is different from a number of the at least some of the plurality of MSBs.

Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in each switch box. The switch boxes are arranged into serial loading sets such that the switch boxes in each serial loading set are configured to form a multi-bit shift register chain for serial shifting the corresponding configuration words.

Abstract: An output switch fabric is disclosed that comprises an interleaved plurality of multiplexers for switching channels between first and second busses. The busses run in tracks that form a grid pattern. The interleaving of the multiplexers is arranged according to the grid pattern for the busses.

Abstract: A memory device having a local current sink is disclosed. In a particular embodiment, an electronic device is disclosed. The electronic device includes one or more write drivers. The electronic device includes at least one Magnetic Tunnel Junction (MTJ) coupled to a bit line and coupled to a source line. The electronic device also includes a current sink circuit comprising a single transistor, the single transistor coupled to the bit line and to the source line.

Abstract: Various aspects of dynamic power reduction in a bus communication architecture are described herein as embodied in an XBAR architecture that provides flexible gating of multiple paths and repeater circuitry to allow any of a number of selected clients to communicate with any of the other interconnected clients while reducing dynamic power consumption by disabling unused repeater circuitry in the bus communication architecture.

Abstract: A memory device having a local current sink is disclosed. In a particular embodiment, an electronic device is disclosed. The electronic device includes one or more write drivers. The electronic device includes at least one Magnetic Tunnel Junction (MTJ) coupled to a bit line and coupled to a source line. The electronic device also includes a current sink circuit comprising a single transistor, the single transistor coupled to the bit line and to the source line.

Abstract: A reconfigurable instruction cell array (RICA) is provided that includes a plurality of master switch boxes that are configured to read and write from a plurality of buffers through a cross-bar switch. A master built-in-self-test (MBIST) engine is configured to drive a test word into the write path of at least one master switch box and to control the cross-bar switch so that the driven test word is broadcast to all the buffers for storage. The MBIST engine is also configured to retrieve the stored test words from the buffers through a read bus within the cross-bar switch.

Abstract: A memory device having a local current sink is disclosed. In a particular embodiment, an electronic device is disclosed. The electronic device includes one or more write drivers. The electronic device includes at least one Magnetic Tunnel Junction (MTJ) coupled to a bit line and coupled to a source line. The electronic device also includes a current sink circuit comprising a single transistor, the single transistor coupled to the bit line and to the source line.

Abstract: A reconfigurable instruction cell array (RICA) is provided that includes a plurality of master switch boxes that are configured to read and write from a plurality of buffers through a cross-bar switch. A master built-in-self-test (MBIST) engine is configured to drive a test word into the write path of at least one master switch box and to control the cross-bar switch so that the driven test word is broadcast to all the buffers for storage. The MBIST engine is also configured to retrieve the stored test words from the buffers through a read bus within the cross-bar switch.

Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in each switch box. The switch boxes are arranged into serial loading sets such that the switch boxes in each serial loading set are configured to form a multi-bit shift register chain for serial shifting the corresponding configuration words.

Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in a latch array for the switch box. The switch boxes are arranged into broadcast sets such that the latch arrays in each broadcast set receive a configuration word in parallel.