Abstract: A hermetic seal is provided for a conductive feedthrough through a thin ceramic component by a platinum or palladium lead by sealing the gap between the lead and the ceramic with a copper-copper oxide eutectic. The lead may have a copper coating on it prior to and subsequent to formation of the copper-copper oxide eutectic.

Abstract: A hermetic seal is provided for a conductive feedthrough through a thin ceramic component by a platinum or palladium lead by sealing the gap between the lead and the ceramic with a copper-copper oxide eutectic. The lead may have a copper coating on it prior to and subsequent to formation of the copper-copper oxide eutectic.

Abstract: A direct (metal-metal compound eutectic) bond process is improved by disposing a eutectic/substrate-wetting enhancement layer on the substrate prior to performing the direct bond process to bond a metal foil to the substrate. Where the metal is copper, the direct bond process is rendered more effective than prior art direct bond processes on alumina and beryllia and makes the direct bond process effective on tungsten, molybdenum and aluminum nitride, all of which were unusable with the prior art direct bond copper process. A variety of new, useful structures may be produced using this process. The eutectic/substrate-wetting enhancement layer is preferably a noble-like metal or includes a noble-like metal such as platinum, palladium and gold.

Abstract: A method of self packaging an integrated circuit chip on a printed circuit board where conductive leads form an electrical connection with interconnect leads on the printed circuit board. A centering frame placed on the printed circuit board serves to align the leads. A cooling cap which dissipates heat from the integrated circuit chip is placed over the centering frame and integrated circuit chip. In one embodiment, the leads form a pressure fit and the cooling cap forces the pressure-fit electrical connections. In another embodiment, the leads make rubbing contact with each other.

Abstract: A method of self packaging an integrated circuit chip (10) on a printed circuit board (14) where conductive leads (16) form an electrical connection with interconnect leads (12) on the printed circuit board (14). A centering frame (22) placed on the printed circuit board serves to align the leads (12 and 16). A cooling cap (34) which dissipates heat from the integrated circuit chip (10) is placed over the centering frame (22) and integrated circuit chip (10). In one embodiment, the leads (12 and 16) form a pressure fit and the cooling cap (34) forces the pressure-fit electrical connections. In another embodiment, the leads (12 and 16) make rubbing contact with each other.

Abstract: A circuit assembly including a plurality of integrated circuit chips wherein electrical interconnections between chips at a relatively large distance from each other are accomplished by a conductor bus comprising a first section including conductors running adjacent and parallel to each other for a distance substantially equal to an integral number of half wavelengths of the base frequency of signals of the circuit and second sections including conductors which sharply diverge toward associated integrated circuit chips for electrical connection therewith.

Abstract: Multilayer circuit boards composed primarily of silicon and containing buried ground planes and buried conducting runs are fabricated in one embodiment by positioning conductive patterns (12) on the surfaces of silicon substrates and melting a solder component of the conductive patterns (12) and allowing it to flow together with solder from the conductive patterns (12) on a stacked, adjacent silicon substrate (10). When the solder cools, a single conductive pathway (18) exists between adjacent silicon substrates (10) and bonds the adjacent substrates. If the substrates are coated with SiO.sub.2 (20), a multilayer structure with buried microwave strip lines (22) is formed in the bonding process. Alternatively, highly resistive silicon substrates (26) are used as a dielectric for microwave strip lines (24) on a top surface thereof and a conductive sheet (28) on the bottom surface thereof acts as a ground plane for microwave energy propagating along strip line (24).

Abstract: A method of self packaging an integrated circuit chip (10) on a printed circuit board (14) where conductive leads (16) form an electrical connection with interconnect leads (12) on the printed circuit board (14). A centering frame (22) placed on the printed circuit board serves to align the leads (12 and 16). A cooling cap (34) which dissipates heat from the integrated circuit chip (10) is placed over the centering frame (22) and integrated circuit chip (10). In one embodiment, the leads (12 and 16) form a pressure fit and the cooling cap (34) forces the pressure-fit electrical connections. In another embodiment, the leads (12 and 16) make rubbing contact with each other.

Abstract: A hermetically sealed package for a power semiconductor wafer is provided comprising substantially entirely silicon materials selected to have coefficients of thermal expansion closely matching that of the power semiconductor wafer. A semiconductor wafer such as a power diode comprises a layer of silicon material having first and second device regions on respective sides thereof. An electrically conductive cap and base, each including a layer of silicon material, are disposed in electrical contact with the first and second regions of the semiconductor device, respectively. An electrically insulative sidewall of silicon material surrounds the semiconductor wafer, is spaced from an edge thereof, and is bonded to the cap and base for hermetically sealing the package. An electrical passivant is disposed on an edge of the semiconductor wafer adjoining the first and second device regions for preventing electrical breakdown between the cap and base.

Abstract: A matched load for an unloaded terminating end of a signal transmission line on a printed circuit wiring board avoids reflecting pulses back down the line. A non-reflective attenuation region is provided under the unloaded terminating end, such region being wedge-shaped and doped to a reduced resistivity, and situated in the silicon substrate of the board. Data pulses at the unloaded terminating end of the transmission line, modulated at the selected operating frequency of the board, are substantially attenuated by the doped region.

Abstract: A thyristor packaging system utilizes structured metal, strain buffers to provide paths of high electrical and thermal conductivity from the anode and cathode of a thyristor to power conductors connected to the anode and the cathode, such strain buffers each comprising a bundle of substantially parallel, closely packed strands of metal wire.

Abstract: A silicon circuit board incorporates multiple levels of patterned conductors. First level upper and lower patterned conductors are situated on an insulation-coated, monocrystalline silicon substrate. Upper and lower, high resistivity, polycrystalline silicon layers, in turn, are situated on the first level upper and lower patterned conductors, respectively. Second level upper and lower patterned conductors are situated over the upper and lower polycrystalline silicon layers. Further levels of patterned conductors in the circuit board may be provided by iteratively forming on the board polycrystalline silicon layers and patterned conductors. Conducting feedthroughs in the circuit board provide electrical communication between various patterened conductors.

Abstract: A first metal surface of a first article of metal, such as the metalization layer on a silicon semiconductor device, is bonded to an opposing or second metal surface of a second article of metal, such as a "structured copper" strain buffer, using an improved method of thermo-compression diffusion bonding that involves temperature control independent of compressional force control, whereby a superior bond is obtained.

Abstract: Methods of forming a conductor pattern including fine conductor runs direct bonded, using a eutectic composition, to a ceramic substrate are disclosed. These methods provide grooves in the side of a metallic sheet to be bonded to the ceramic substrate, the grooves serving as vent passages for any otherwise entrapped gas between the metallic sheet and the ceramic substrate.

Abstract: A semiconductor electronic device operates at high power levels using structured copper to reduce generation of stress between the elements of the device during thermal cycling in the course of normal operation. Structured copper strain buffers are used to attach each side of a silicon wafer to fluid cooled heat sinks to provide efficient removal of heat generated by the device and good electrical connection to the silicon wafer.

Abstract: A method for storing data in an archival memory semiconductor target by providing a masking layer of a conductive material on the surface of an insulative layer upon the top surface of a semiconductor substrate; the material layer is assigned a two-dimensional array of possible data storage sites. The masking layer at those storage sites at which a first binary value is to be stored, is melted; the selected material is one which, at the melting temperature thereof, does not wet the surface of the chosen insulator whereby apertures are formed by the writing electron beam in the masking layer, at energy levels insufficient to evaporate the masking material. The writing beam energy is reduced at the data sites at which data bits of the remaining binary value are to be stored, and does not melt the masking material thereat.

Abstract: The bond between a structured copper heat sink member and a semiconductor wafer is inspected for voids and unbonds by a focused ultrasonic pulse transmission method. The small focused spot of ultrasound is transmitted along the structured copper strands and is attenuated in the lateral direction. The absence of a received pulse or a significantly reduced amplitude signal, as the assembled device is scanned with acoustic pulses, indicate flaws in the bond.

Abstract: Concentrated sunlight impinges on a large area photovoltaic device which is bonded to a highly pliable and thermally and electrically conductive structured copper strain relieving member; the lower face of the structured copper is sealed to a fluid cooled metal heat sink. Large power densities of sunlight are absorbed without appreciable temperature rise. The structured copper accommodates to the difference in expansion between the metal heat sink and the semiconductor wafer. Three embodiments utilize a single planar junction diode, an interdigitated diode, and series connected isolated junction diodes.

Abstract: A method for storing data in an archival memory semiconductor target by providing a masking layer of a conductive material on the surface of an insulative layer upon the top surface of a semiconductor substrate; the material layer is assigned a two-dimensional array of possible data storage sites. The masking layer at those storage sites at which a first binary value is to be stored, is melted; the selected material is one which, at the melting temperature thereof, does not wet the surface of the chosen insulator whereby apertures are formed by the writing electron beam in the masking layer, at energy levels insufficient to evaporate the masking material. The writing beam energy is reduced at the data sites at which data bits of the remaining binary value are to be stored, and does not melt the masking material thereat.

Abstract: Radiation sensitive switches which undergo thermal decomposition to physically interrupt the circuit path when activated are operatively associated with a plurality of high voltage flash lamps utilizing a shorting primer material to provide an electrical path across said lamps after flashing as the means of enabling the flash lamps to be sequentially flashed in a high-voltage activated multiple flash lamp array. The thermal decomposition of the radiation sensitive switching elements produces self-destruction of the switch elements per se and which can be accompanied by further destruction of the underlying substrate on which the switch elements have been deposited. The switching elements are deposited on a circuit board member and electrically connected in the sequential lamp firing circuitry at circuit board locations adjacent to the associated flash lamps.