Patents by Inventor Harold W. Dozier

Harold W. Dozier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8315175
    Abstract: Instead of alternatively utilizing only one fabric or the other fabric of a redundant pair, both fabrics simultaneously transmit duplicate information, such that each packet forwarding module (PFM) receives the output of both fabrics simultaneously. In real time, an internal optics module (IOM) analyzes each information chunk coming out of a working zero switch fabric; simultaneously examines a parallel output of a working one duplicate switch fabric; and compares on a chunk-by-chunk basis the validity of each and every chunk from both switch fabrics. The IOM does this by examining forward error correction (FEC) check symbols encapsulated into each chunk. FEC check symbols allow correcting a predetermined number of bit errors within a chunk. If the chunk cannot be corrected, then the IOM provides indication to all PFMs downstream that the chunk is defective. Under such conditions, the PFMs select a chunk from the non-defective switch fabric.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: November 20, 2012
    Assignee: Foundry Networks, LLC
    Inventors: Thomas C. McDermott, III, Harry C. Blackmon, Tony M. Brewer, Harold W. Dozier, Jim Kleiner, Gregory S. Palmer, Keith W. Shaw, David Traylor, Dean E. Walker
  • Patent number: 8279879
    Abstract: A chunk format for a large-scale, high data throughput router includes a preamble that allows each individual chunk to have clock and data recovery performed before the chunk data is retrieved. The format includes a chunk header that contains information specific to the entire chunk. A chunk according to the present format can contain multiple packet segments, with each segment having its own packet header for packet-specific information. The format provides for a scrambler seed which allows scrambling the data to achieve a favorable zero and one balance as well as minimal run lengths. There can be a random choice of available scrambler seeds for any particular chunk to avoid malicious forcing of zero and one patterns or run lengths of bit zeroes and ones. There are a chunk cyclical redundancy check (CRC) as well as forward error correction (FEC) bytes to detect and/or correct any errors and also to insure a high degree of data and control integrity.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: October 2, 2012
    Assignee: Foundry Networks, LLC
    Inventors: Tony M. Brewer, Harry C. Blackmon, Chris Davies, Harold W. Dozier, Thomas C. McDermott, III, Steven J. Wallach, Dean E. Walker, Lou Yeh
  • Patent number: 7613183
    Abstract: A chunk format for a large-scale, high data throughput router includes a preamble that allows each individual chunk to have clock and data recovery performed before the chunk data is retrieved. The format includes a chunk header that contains information specific to the entire chunk. A chunk according to the present format can contain multiple packet segments, with each segment having its own packet header for packet-specific information. The format provides for a scrambler seed which allows scrambling the data to achieve a favorable zero and one balance as well as minimal run lengths. There are forward error correction (FEC) bytes as well as a chunk cyclical redundancy check (CRC) to detect and/or correct any errors and also to insure a high degree of data and control integrity. Advantageously, a framing symbol inserted into the chunk format itself allows the receiving circuitry to identify or locate a particular chunk format.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: November 3, 2009
    Assignee: Foundry Networks, Inc.
    Inventors: Tony M. Brewer, Harry C. Blackmon, Chris Davies, Harold W. Dozier, Thomas C. McDermott, III, Steven J. Wallach, Dean E. Walker, Lou Yeh
  • Patent number: 7324500
    Abstract: A router line card is partitioned to separate the packet forwarding functions from physical port interfacing. For each packet forwarding card, at least one redundant port interface is provided. Identical input packets are transmitted via these redundant input port interfaces, one of which is eventually selected based on, for example, SONET standard criteria. If there is a failure, the router selects the interface path that is operating properly and rejects the path containing a failed element. Thus, the router decides locally how to correct the problem internally. Moreover, following an equipment failure the now offline failed interface path can be replaced, while the equipment remains in service using the duplicated interface path. The system can be restored to full duplex operation without affecting the existing traffic, providing for a hot replacement of a failed path. Because the interfaces are separate, a failed module can be renewed and replaced while the equipment is in service.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: January 29, 2008
    Assignee: Jeremy Benjamin as Receiver for Chiaro Networks Ltd.
    Inventors: Harry C. Blackmon, Tony M. Brewer, Harold W. Dozier, Thomas C. McDermott, III, Gregory S. Palmer
  • Patent number: 6894970
    Abstract: Instead of alternatively utilizing only one fabric or the other fabric of a redundant pair, both fabrics simultaneously transmit duplicate information, such that each packet forwarding module (PFM) receives the output of both fabrics simultaneously. In real time, an internal optics module (IOM) analyzes each information chunk coming out of a working zero switch fabric; simultaneously examines a parallel output of a working one duplicate switch fabric; and compares on a chunk-by-chunk basis the validity of each and every chunk from both switch fabrics. The IOM does this by examining forward error correction (FEC) check symbols encapsulated into each chunk. FEC check symbols allow correcting a predetermined number of bit errors within a chunk. If the chunk cannot be corrected, then the IOM provides indication to all PFMs downstream that the chunk is defective. Under such conditions, the PFMs select a chunk from the non-defective switch fabric.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: May 17, 2005
    Assignee: Chiaro Networks, Ltd.
    Inventors: Thomas C. McDermott, III, Harry C. Blackmon, Tony M. Brewer, Harold W. Dozier, Jim Kleiner, Gregory S. Palmer, Keith W. Shaw, David Traylor, Dean E. Walker
  • Patent number: 6879559
    Abstract: Router line cards are partitioned, separating packet forwarding from external or internal interfaces and enabling multiple line cards to access any set of external or internal data paths. Any failed working line card can be switchably replaced by another line card. In particular, a serial bus structure on the interface side interconnects any interface port within a protection group with a protect line card for that group. Incremental capacity allows the protect line card to perform packet forward functions. Logical mapping of line card addressing and identification provides locally managed protection switching of a line card that is transparent to other router line cards and to all peer routers. One-for-N protection ratios, where N is some integer greater than two, can be achieved economically, yet provide sufficient capacity with acceptable protection switch time under 100 milliseconds.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: April 12, 2005
    Assignee: Chiaro Networks, Ltd.
    Inventors: Harry C. Blackmon, Tony M. Brewer, Harold W. Dozier, Jim Kleiner, Thomas C. McDermott, III, Gregory S. Palmer, Keith W. Shaw, David Traylor
  • Patent number: 6711357
    Abstract: Information and control are synchronized as they flow through a large distributed IP router system with independent clocks. The IP router includes multiple equipment racks and shelves, each containing multiple modules. The IP router is based on a passive switching device, which in some embodiments is an optical switch. Control and data come to the switching device from different sources, which have different clocks. Timing and synchronization control are provided, such that information and control both arrive at the switching device at the proper time. A single point in the system originates timing, which is then distributed through various ASICs of the system to deliver configuration control to the switch at the appropriate time. The launch of information to the switch is also controlled with a dynamic feedback loop from an optical switch controller. Control aspects of the optical switch are aligned by this same mechanism to deliver control and data to the optical switch simultaneously.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: March 23, 2004
    Assignee: Chiaro Networks Ltd.
    Inventors: Tony Brewer, Harry C. Blackmon, Harold W. Dozier, William D. O'Leary, Dean E. Walker
  • Patent number: 6061222
    Abstract: A method and apparatus for reducing noise in integrated circuit chips (ICs). The apparatus comprises on-die capacitance in conjunction with one or more resistive loss elements, which provide an AC termination for on-die power events. The on-die capacitance can be instantiated in metal layers alone, in gate oxides or in gate oxides combined with metal structures. The capacitance may be provided by the capacitive characteristics of adjacent metal layers of the power distribution structure of the IC. When the capacitance is provided in this manner, the resistive loss element corresponds to the linear resistance of thin lines on the metal layers of the power distribution structure. The resistive loss element may, alternatively, be comprised of a field effect transistor (FET) or a metal oxide semiconductor field effect transistor (MOSFET).
    Type: Grant
    Filed: August 28, 1998
    Date of Patent: May 9, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Terrel L. Morris, Harold W. Dozier
  • Patent number: 4809171
    Abstract: An operand processing unit (10) carries out processing of operands in a computer. The unit (10) includes a plurality of operation circuits (12, 14, 16, 18, 20). A source bus (22) provides one operand per clock cycle to the operation circuits (12, 14, 16, 18, 20). A destination bus (24) receives one resultant per clock cycle from the operation circuits (12, 14, 16, 18, 20). Within each operation circuit there is provided an operand processing circuit (80) which performs a selected function with the received operands. These functions include, for example, multiplication, division, addition, subtraction, logical AND, and shift. Logical circuitry provides a priority assignment to the operation circuits (12, 14, 16, 18, 20) for sequencing the loading of operands into the highest priority operation circuit (12, 14, 16, 18, 20) which is not busy processing operands within its corresponding operand processing circuit (80).
    Type: Grant
    Filed: January 21, 1988
    Date of Patent: February 28, 1989
    Assignee: Convex Computer Corporation
    Inventors: Harold W. Dozier, Thomas M. Jones, Steven J. Wallach, Jeffrey H. Gruger
  • Patent number: 4704599
    Abstract: An auxiliary connector circuit is used within an electronic system (10) which comprises a plurality of removable circuit cards (14, 16, 18, 20, 22, 24, 26) which are mounted within a cabinet (12). Before the circuit card (16) is removed from the cabinet (12), a power cable (44) is connected by means of engaging a plug (46) to a socket (34). When this occurs a DATA OUT ENABLE signal at a line (65) drives three-state devices (86, 88, 90, 92, 94, 96, 98 and 100) to a high impedance state to isolate a memory array (78) from a data bus (102). This high impedance prevents any transients from being transmitted through the data bus (102) when the card (16) is removed from the cabinet (12). After the card (16) is removed from the cabinet (12), the power cable (44) can be disconnected from the card (16) or the card (16) can be tested to evaluate the components mounted on the card (16).
    Type: Grant
    Filed: June 20, 1984
    Date of Patent: November 3, 1987
    Inventors: Arthur T. Kimmel, Harold W. Dozier
  • Patent number: 4620275
    Abstract: A vector processing computer is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main memory, a physical cache unit or a logical cache through a source bus where the elements are alternately loaded into the vector processing units. The vector control unit decodes the vector instructions and generates the required control commands for operating the registers and logical units within the vector processing units. Thus, the vector processing units essentially work in parallel to double the processing rate. The resulting vectors are transmitted through a destination bus to either the physical cache unit, the main memory, the logical cache or to an input/output processor.
    Type: Grant
    Filed: June 20, 1984
    Date of Patent: October 28, 1986
    Inventors: Steven J. Wallach, Thomas M. Jones, Frank J. Marshall, David A. Nobles, Kent A. Fuka, Steven M. Rowan, William H. Wallace, Harold W. Dozier, David M. Chastain, John W. Clark, Robert B. Kolstad, James E. Mankovich, Michael C. Harris, Jeffrey H. Gruger, Alan D. Gant, Harold D. Shelton, James R. Weatherford, Arthur T. Kimmel, Gary B. Gostin, Gilbert J. Hansen, John M. Golenbieski, Larry W. Spry, Gerald Matulka, Gaynel J. Lockhart, Michael E. Sydow
  • Patent number: 4609985
    Abstract: A microcomputer has provision for both on-chip ROM (on the same chip as the CPU) and off-chip ROM and which may operate with only on-chip ROM as only off-chip ROM has the hardware capability to disable on-chip ROM permanently, so that chips having defective ROM may be salvaged by being converted to computer chips that use only off-chip ROM.
    Type: Grant
    Filed: December 30, 1982
    Date of Patent: September 2, 1986
    Assignee: Thomson Components-Mostek Corporation
    Inventor: Harold W. Dozier
  • Patent number: 4472871
    Abstract: An integrated circuit using MOSFETs having varying threshold voltages permitting improved performance and reduced area utilization on a monolithic semiconductor chip is produced by selectively varying ion implantation doses in the channels of the MOSFETs. By repeated masking and implanting steps, selected MOSFETs are implanted with differing doses of ions and combinations of doses, thereby forming circuit portions with MOSFETs having threshold voltages tailored to optimize different characteristics associated with different circuit portions.
    Type: Grant
    Filed: November 19, 1980
    Date of Patent: September 25, 1984
    Assignee: Mostek Corporation
    Inventors: Robert S. Green, Harold W. Dozier, Vernon D. McKenny
  • Patent number: 4348743
    Abstract: A microcomputer which is implemented by MOS/LSI techniques on a single semiconductor chip is disclosed. The computer includes a data processing system having control logic means, means for exchanging data with peripheral devices through at least one data transfer port, an ALU, and program storage means in which a set of microprograms are stored including at least a first microprogram for controlling the execution of instructions issued from the control logic means. A binary timer is provided which permits operation in an interval timer mode, a pulse width measurement mode, and an event counter mode. The binary timer cooperates with an interrupt logic unit to process an interrupt request in response to time-out signals from the binary timer, and also in response to an external interrupt request.
    Type: Grant
    Filed: February 13, 1981
    Date of Patent: September 7, 1982
    Assignee: Mostek Corporation
    Inventor: Harold W. Dozier
  • Patent number: 4317275
    Abstract: A switch for selecting internal circuit options in MOS/LSI circuits without altering the circuit layout on a semiconductor chip by selectively implanting channels of field-effect transistors such that selected circuit-option lines are coupled to a designated line. Switches may be constructed with multiple inputs and a single output, or with multiple outputs and a single input, or with multiple inputs and multiple outputs. A bidirectional switch may also be constructed by controlling the gate potential of each transistor connecting one of the option lines to the designated line with a two-input switch for selecting either a high or a low gate potential.
    Type: Grant
    Filed: January 10, 1980
    Date of Patent: March 2, 1982
    Assignee: Mostek Corporation
    Inventor: Harold W. Dozier
  • Patent number: 4204131
    Abstract: A switch for selecting internal circuit options in MOS/LSI circuits without altering the circuit layout on a semiconductor chip by selectively implanting channels of field-effect transistors such that selected circuit-option lines are coupled to a designated line. Switches may be constructed with multiple inputs and a single output, or with multiple outputs and a single input, or with multiple inputs and multiple outputs. A bidirectional switch may also be constructed by controlling the gate potential of each transistor connecting one of the option lines to the designated line with a two-input switch for selecting either a high or a low gate potential.
    Type: Grant
    Filed: October 11, 1977
    Date of Patent: May 20, 1980
    Assignee: Mostek Corporation
    Inventor: Harold W. Dozier
  • Patent number: 4142176
    Abstract: A read only memory (ROM) structure in which a plurality of enhancement and depletion transistors are organized into a series-connected NAND logic matrix. The usual metal-to-diffusion contacts required for every one or two bits, as well as interweaved power supply lines required for every two row lines in conventional NOR logic circuits are not used in the series arrangement thereby minimizing the geometry of the ROM structure. In a preferred embodiment, logical information is stored within the ROM matrix by means of silicon gate metal oxide semiconductor field effect transistors which are arranged into a matrix having a number of common gate input rows and a number of series connected output columns which correspond to selected logic combinations of the inputs. The logical content of individual memory cells within the matrix is determined by providing either enhancement mode or depletion mode MOSFET transistors as elements of the matrix.
    Type: Grant
    Filed: September 27, 1976
    Date of Patent: February 27, 1979
    Assignee: Mostek Corporation
    Inventor: Harold W. Dozier
  • Patent number: 4135102
    Abstract: The invention disclosed herein is a high performance inverter circuit using MOSFETs having varying threshold voltages produced by selectively varying ion implantation doses in the channels of the MOSFETs and using a slightly depletion type MOSFET, rather than a conventional depletion type, in the output stage.
    Type: Grant
    Filed: July 18, 1977
    Date of Patent: January 16, 1979
    Assignee: Mostek Corporation
    Inventors: Robert S. Green, Harold W. Dozier, Vernon G. McKenny