Patents by Inventor Harold William Satterfield

Harold William Satterfield has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10158281
    Abstract: In an embodiment, a power-supply controller includes a control circuit, a drive circuit, and a signal-drop-reducing circuit. The control circuit is configured to generate a drive signal having a duty cycle, and the drive circuit is configured to cause a phase circuit of a power supply to generate, in response to the drive signal, an output signal having a magnitude. And the signal-drop-reducing circuit is configured to disable the driver circuit in response to the duty cycle corresponding to a signal magnitude that is lower than the magnitude of the output signal. For example, where a power supply has a non-zero residual output signal (e.g., output voltage) on its output node after the power supply is deactivated, such a power-supply controller can reduce or eliminate a drop in the residual output signal caused by, or that would be caused by, a restarting of the power supply.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: December 18, 2018
    Assignee: INTERSIL AMERICAS LLC
    Inventors: Harold William Satterfield, James White
  • Patent number: 10044256
    Abstract: In an embodiment, a method includes generating a pulse-width-modulated signal having a duty cycle, and isolating a power-supply output node in response to the duty cycle corresponding to a signal magnitude that is less than a magnitude of an output signal on the power-supply output node. For example, where a power supply has a non-zero residual output signal (e.g., output voltage) on its output node after the power supply is deactivated, a power-supply controller can use such a technique to reduce or eliminate a drop in the residual output signal caused by, or that would be caused by, a restarting of the power supply.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: August 7, 2018
    Assignee: INTERSIL AMERICAS LLC
    Inventors: Harold William Satterfield, James White
  • Publication number: 20170077809
    Abstract: In an embodiment, a power-supply controller includes a control circuit, a drive circuit, and a signal-drop-reducing circuit. The control circuit is configured to generate a drive signal having a duty cycle, and the drive circuit is configured to cause a phase circuit of a power supply to generate, in response to the drive signal, an output signal having a magnitude. And the signal-drop-reducing circuit is configured to disable the driver circuit in response to the duty cycle corresponding to a signal magnitude that is lower than the magnitude of the output signal. For example, where a power supply has a non-zero residual output signal (e.g., output voltage) on its output node after the power supply is deactivated, such a power-supply controller can reduce or eliminate a drop in the residual output signal caused by, or that would be caused by, a restarting of the power supply.
    Type: Application
    Filed: March 21, 2016
    Publication date: March 16, 2017
    Inventors: Harold William Satterfield, James White
  • Publication number: 20170077816
    Abstract: In an embodiment, a method includes generating a pulse-width-modulated signal having a duty cycle, and isolating a power-supply output node in response to the duty cycle corresponding to a signal magnitude that is less than a magnitude of an output signal on the power-supply output node. For example, where a power supply has a non-zero residual output signal (e.g., output voltage) on its output node after the power supply is deactivated, a power-supply controller can use such a technique to reduce or eliminate a drop in the residual output signal caused by, or that would be caused by, a restarting of the power supply.
    Type: Application
    Filed: March 21, 2016
    Publication date: March 16, 2017
    Inventors: Harold William Satterfield, James White
  • Patent number: 8327248
    Abstract: A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as the test signals. In response to a number of logic combinations of the test signals, the voter generates output signals each corresponding to one of the redundant channel signals. In response to other logic combinations of the test signals, the voter generates a voted output signal. The voter is optionally a majority voter.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: December 4, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Harold William Satterfield, Grady M. Wood
  • Patent number: 8299768
    Abstract: A pulse-width modulated (PWM) DC-DC converter has a multitude of redundant channels supplying PWM signals to a voter whose output voltage controls the regulated DC output voltage. To ensure that single transient events, single permanent faults, or mismatches in the electrical characteristics of the various components disposed in the redundant channels do not adversely affect the regulated DC output voltage, transitions of the PWM signal in each channel are compared to the corresponding transitions of the voter's output signal. If a PWM signal transition of a redundant channel is detected as occurring relatively earlier/later than the corresponding transition of the voter's output signal, the width of the PWM signal is increased/decreased. If a PWM signal transition of a redundant channel is detected as occurring within a predefined window of the corresponding transition of the voter's output signal, the width of the PWM signal is not changed.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: October 30, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Harold William Satterfield, Lawrence Pearce
  • Publication number: 20120272109
    Abstract: A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as the test signals. In response to a number of logic combinations of the test signals, the voter generates output signals each corresponding to one of the redundant channel signals. In response to other logic combinations of the test signals, the voter generates a voted output signal. The voter is optionally a majority voter.
    Type: Application
    Filed: June 22, 2012
    Publication date: October 25, 2012
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Harold William Satterfield, Grady Wood
  • Publication number: 20120262208
    Abstract: A clock generation circuit, includes, in part, a comparator, a logic unit, and a switching circuit. The switching circuit generates a signal that is applied to the comparator. If the input voltage level of the signal applied to the comparator is greater than a first reference voltage, the comparator asserts its first output signals. If the input voltage level of the signal applied to the comparator is less than a second reference voltage, the comparator asserts its second output signal. The output signals of the comparator form a first pair of feedback signals applied to the switching circuit. The logic unit responds to the output signals of the comparator to generate a second pair of oscillating feedback signals that are also applied to the switching circuit. The switching circuit varies a capacitor voltage in response to a reference current and in response to the two pairs of feedback signals it receives.
    Type: Application
    Filed: June 22, 2012
    Publication date: October 18, 2012
    Applicant: INTERSIL AMERICAS INC.
    Inventor: Harold William Satterfield
  • Patent number: 8217697
    Abstract: A clock generation circuit, includes, in part, a comparator, a logic unit, and a switching circuit. The switching circuit generates a signal that is applied to the comparator. If the input voltage level of the signal applied to the comparator is greater than a first reference voltage, the comparator asserts its first output signals. If the input voltage level of the signal applied to the comparator is less than a second reference voltage, the comparator asserts its second output signal. The output signals of the comparator form a first pair of feedback signals applied to the switching circuit. The logic unit responds to the output signals of the comparator to generate a second pair of oscillating feedback signals that are also applied to the switching circuit. The switching circuit varies a capacitor voltage in response to a reference current and in response to the two pairs of feedback signals it receives.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: July 10, 2012
    Assignee: Intersil Americas Inc.
    Inventor: Harold William Satterfield
  • Patent number: 8209591
    Abstract: A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as the test signals. In response to a number of logic combinations of the test signals, the voter generates output signals each corresponding to one of the redundant channel signals. In response to other logic combinations of the test signals, the voter generates a voted output signal. The voter is optionally a majority voter.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: June 26, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Harold William Satterfield, Grady Wood
  • Publication number: 20100127680
    Abstract: A pulse-width modulated (PWM) DC-DC converter has a multitude of redundant channels supplying PWM signals to a voter whose output voltage controls the regulated DC output voltage. To ensure that single transient events, single permanent faults, or mismatches in the electrical characteristics of the various components disposed in the redundant channels do not adversely affect the regulated DC output voltage, transitions of the PWM signal in each channel are compared to the corresponding transitions of the voter's output signal. If a PWM signal transition of a redundant channel is detected as occurring relatively earlier/later than the corresponding transition of the voter's output signal, the width of the PWM signal is increased/decreased. If a PWM signal transition of a redundant channel is detected as occurring within a predefined window of the corresponding transition of the voter's output signal, the width of the PWM signal is not changed.
    Type: Application
    Filed: November 19, 2009
    Publication date: May 27, 2010
    Applicant: Intersil Americas Inc.
    Inventors: Harold William Satterfield, Lawrence Pearce
  • Publication number: 20100127679
    Abstract: A clock generation circuit, includes, in part, a comparator, a logic unit, and a switching circuit. The switching circuit generates a signal that is applied to the comparator. If the input voltage level of the signal applied to the comparator is greater than a first reference voltage, the comparator asserts its first output signals. If the input voltage level of the signal applied to the comparator is less than a second reference voltage, the comparator asserts its second output signal. The output signals of the comparator form a first pair of feedback signals applied to the switching circuit. The logic unit responds to the output signals of the comparator to generate a second pair of oscillating feedback signals that are also applied to the switching circuit. The switching circuit varies a capacitor voltage in response to a reference current and in response to the two pairs of feedback signals it receives.
    Type: Application
    Filed: November 17, 2009
    Publication date: May 27, 2010
    Applicant: Intersil Americas Inc.
    Inventor: Harold William Satterfield
  • Publication number: 20100106448
    Abstract: A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as the test signals. In response to a number of logic combinations of the test signals, the voter generates output signals each corresponding to one of the redundant channel signals. In response to other logic combinations of the test signals, the voter generates a voted output signal. The voter is optionally a majority voter.
    Type: Application
    Filed: October 22, 2009
    Publication date: April 29, 2010
    Applicant: INTERSIL AMERCAS INC.
    Inventors: Harold William Satterfield, Grady Wood