Abstract: A serial to parallel converter receives a succession of digital bits in serial form comprising discrete data formats and control formats through its input terminal, which is coupled to a data shift register and to a control shift register. When a data format is coupled into the input, a register enable circuit enables the data register to load and convert sets of changeable data bits, comprising part of the data format, to parallel form. When a control format is coupled into the input, the register enable circuit enables the control shift register to convert sets of changeable control bits, comprising part of the control format, to parallel form. One of the changeable bits in every control format immediately followed by a data format comprises an incoming data indicator.

Abstract: A data switch which can rapidly configure and reconfigure multiple channels between computer equipments for digital data transmitted at a rate in excess of 10 megabits per second. The switch includes a switch matrix connected between an input and an output voltage level buffer, a mini computer, and control circuitry. The switch matrix comprises three stages, each containing 256 switching elements which are active integrated circuit elements each having 16 data inputs and one data output. A channel is configured through the switch matrix when one switching element in each stage responds to a control signal to couple one of its data inputs to its data output, over a million different channel configurations being possible. Each switching element is heavily grounded to effectively eliminate cross talk between channels and each data input line of each switching element is provided with an amplifier to improve time fidelity of the switch.

Abstract: A switching system for rapidly configuring transmission paths between comer equipments for high speed digital information in parallel form couples the input of a parallel-to-serial (P/S) converter to the output of each equipment providing information and the output of a serial-to-parallel (S/P) converter to the input of each equipment receiving information. A digital switch rapidly configures information transmission channels between its inputs and outputs in response to instructions from a configuration control. Each switch input is coupled to the output of a P/S converter, and each switch output is coupled through a switch output lead to the input of an S/P converter. A clock provides a periodic clock signal to each P/S converter through an adjustable delay control and to each S/P converter through a clock lead, wherein the electrical lengths of the switch output lead and clock lead coupled to the same S/P converter are equal.

Abstract: A high speed parallel to serial digital converter includes a data shift rster, a control shift register and control circuitry. During a control cycle a control input comprising a set of control bits in parallel form is converted by the control shift register into serial form. The serialized control bits are coupled to a register load selector which responds to the control bits to appropriately signal the control circuitry so that at the end of the control cycle the converter will commence either another control cycle or a data cycle. During a data cycle an input data word comprising data bits in parallel form is converted by the data shift register into serial form. At the end of a data cycle timing circuitry signals the control circuitry to commence a reset cycle during which the converter is reset to commence another control cycle.