Abstract: A lot dispatching method and apparatus for dispatching WIP lots in the manufacture of semiconductor integrated circuits includes determining an average process time (T) and average number of lots per batch (a) of a succeeding process, and determining allowable lots (k) of a preceding process. The allowable lots (k) is equal to the preceding lots (m) undergoing the preceding process to the extent that the sum of (m) and the lots waiting to undergo the succeeding process (n) is not greater than the maximum batch size of the succeeding process. An allowable waiting time is then determined in accordance with a lot waiting rule, where the allowable waiting time represents the average time for processing the number of additional lots to be gained by waiting for the preceding process to complete. The allowable waiting time is determined by the equation k(T/a).