Abstract: A logical NAND memory architecture comprising two-terminal, non-volatile resistive memory is disclosed. By way of example, disclosed logical NAND architectures can comprise non-volatile memory cells having approximately 4 F2 area. This facilitates very high memory densities, even for advanced technology nodes. Further, the disclosed architectures are CMOS compatible, and can be constructed among back-end-of-line (BEOL) metal layers of an integrated chip. In some embodiments, subsets of two-terminal memory cells in a NAND array can be constructed between different pairs of BEOL metal layers. In other embodiments, the two-terminal memory cells can be constructed between a single pair of BEOL metal layers.

Abstract: A logical NAND memory architecture comprising two-terminal, non-volatile resistive memory is disclosed. By way of example, disclosed logical NAND architectures can comprise non-volatile memory cells having approximately 4F2 area. This facilitates very high memory densities, even for advanced technology nodes. Further, the disclosed architectures are CMOS compatible, and can be constructed among back-end-of-line (BEOL) metal layers of an integrated chip. In some embodiments, subsets of two-terminal memory cells in a NAND array can be constructed between different pairs of BEOL metal layers. In other embodiments, the two-terminal memory cells can be constructed between a single pair of BEOL metal layers.

Abstract: Providing for a memory device having a resistive switching memory integrated within backend layers of the memory device is described herein. By way of example, the resistive switching memory can be embedded memory such as cache, random access memory, or the like, in various embodiments. The resistive memory can be fabricated between various backend metallization schemes, including backend copper metal layers and in part utilizing one or more damascene processes. In some embodiments, the resistive memory can be fabricated in part with damascene processes and in part with subtractive etch processing, utilizing four or fewer photo-resist masks. Accordingly, the disclosure provides a relatively low cost, high performance embedded memory compatible with a variety of fabrication processes of integrated circuit foundries.

Abstract: A memory cell that includes a first metal layer formed over a substrate is provided. The substrate includes one or more complementary metal-oxide semiconductor devices. The memory cell also includes a via device that connects at least a portion of the first metal layer and at least another portion of a second metal layer. The first metal layer has a first thickness having an edge thereof that serves as an electrode for a memory cell formed by the via device. The memory cell scales as a function of the first thickness and at least in part independent of a minimum feature size of the memory device.

Abstract: A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode.

Abstract: A recessed high voltage metal oxide semiconductor (MOS) transistor is provided for use in a two-terminal memory cell. The two-terminal memory cell can include a resistive switching device connected to the recessed MOS transistor. The recessed MOS transistor provides for an increased channel length relative to the transistor size in comparison to a traditional MOS transistor. This allows for a decreased memory cell size while maintaining comparable electrical parameters (threshold voltage, channel length, and leakage) than would otherwise be possible. The recessed MOS transistor can be made as either a NMOS or PMOS device using n-type or p-type materials respectively, where the channel, or inversion layer, is formed by electrons (NMOS) or holes (PMOS) between the source and drain in the transistor.

Abstract: A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode.

Abstract: Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer.

Abstract: A two-terminal memory device can be formed according to a manufacturing process that utilizes two distinct chemical-mechanical planarization (CMP) processes for each of bottom electrode/terminal (BE) and the top electrode/terminal (TE). The CMP processes can reduce planar height variations for a top surface of the BE and a top surface of the TE. The CMP processes can reduce height differences between the top surface of the BE and adjacent dielectric surfaces and reduce height differences between the top surface of the TE and adjacent dielectric surfaces.

Abstract: Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer.

Abstract: A high density non-volatile memory device is provided that uses one or more volatile elements. In some embodiments, the non-volatile memory device can include a resistive two-terminal selector that can be in a low resistive state or a high resistive state depending on the voltage being applied. A deep trench MOS (“metal-oxide-semiconductor”) transistor having a floating gate with small area relative to conventional devices can be provided, in addition to a capacitor or transistor acting as a capacitor. A first terminal of the capacitor can be connected to a voltage source, and the second terminal of the capacitor can be connected to the selector device. The small area floating gate of the deep trench transistor can be connected to the other side of the selector device, and a second transistor can be connected in series with the deep trench transistor.

Abstract: A circuit operable as a non-volatile memory cell, formed in part from a volatile selection device, is provided. The circuit can be fabricated utilizing Integrated Circuit (IC)-Foundry compatible processes to simplify manufacturing, reduce cost and improve yield. For instance, the circuit can comprise a set of transistors fabricated at least in part with front-end-of-line IC processes, and can comprise the volatile selection device and a set of interconnects fabricated at least in part with back-end-of-line IC processes. In further embodiments, the volatile selection device can be a two-terminal, volatile resistive-switching device connected at one end to a gate of an n-well transistor, and connected at a second end to a gate of a p-well transistor.

Abstract: Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichiometric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiOX, where X can be a non-integer greater than zero and less than 2. The sub-oxide can be created in a variety of ways, including various techniques related to growing the sub-oxide, depositing the sub-oxide, or transforming an extant film into the sub-oxide.

Abstract: A method includes patterning a layered structure comprising a monolithic stack including a bottom electrode surrounded by a dielectric material, a switching material, a barrier material, a dielectric hardmask, and a patterned photoresist formed above and adjacent to a portion of the dielectric hardmask. The patterning includes patterning the dielectric hardmask using a first etchant and employing the patterned photoresist as a mask, patterning the barrier material using a second etchant and employing a portion of the dielectric hardmask remaining after the patterning the dielectric hardmask as a mask, and patterning the switching material using ion milling or etching and employing the portion of the dielectric hardmask remaining after the patterning the barrier material as a mask.

Abstract: A memory device comprising a doped conductive polycrystalline layer having an electrically resistive portion, is described herein. By way of example, ion implantation to a subset of the conductive polycrystalline layer can degrade and modify the polycrystalline layer, forming the electrically resistive portion. The electrically resistive portion can include resistive switching properties facilitating digital information storage. Parametric control of the ion implantation can facilitate control over corresponding resistive switching properties of the resistive portion. For example, a projected range or depth of the ion implantation can be controlled, allowing for preferential placement of atoms in the resistive portion, and fine-tuning of a forming voltage of the memory device. As another example, dose and number of atoms implanted, type of atoms or ions that are implanted, the conductive polycrystalline material used, and so forth, can facilitate control over switching characteristics of the memory device.

Abstract: In one embodiment, an ESD device is configured to include a trigger device that assists in forming a trigger of the ESD device. The trigger device is configured to enable a transistor or a transistor of an SCR responsively to an input voltage having a value that is no less than the trigger value of the ESD device.

Abstract: A recessed high voltage metal oxide semiconductor (MOS) transistor is provided for use in a two-terminal memory cell. The two-terminal memory cell can include a resistive switching device connected to the recessed MOS transistor. The recessed MOS transistor provides for an increased channel length relative to the transistor size in comparison to a traditional MOS transistor. This allows for a decreased memory cell size while maintaining comparable electrical parameters (threshold voltage, channel length, and leakage) than would otherwise be possible. The recessed MOS transistor can be made as either a NMOS or PMOS device using n-type or p-type materials respectively, where the channel, or inversion layer, is formed by electrons (NMOS) or holes (PMOS) between the source and drain in the transistor.

Abstract: A high density non-volatile memory device is provided that uses one or more volatile elements. In some embodiments, the non-volatile memory device can include a resistive two-terminal selector that can be in a low resistive state or a high resistive state depending on the voltage being applied. A deep trench MOS (“metal-oxide-semiconductor”) transistor having a floating gate with small area relative to conventional devices can be provided, in addition to a capacitor or transistor acting as a capacitor. A first terminal of the capacitor can be connected to a voltage source, and the second terminal of the capacitor can be connected to the selector device. The small area floating gate of the deep trench transistor can be connected to the other side of the selector device, and a second transistor can be connected in series with the deep trench transistor.

Abstract: During fabrication of a two-terminal memory device, a terminal (e.g., bottom terminal) can be formed. After formation of the terminal, a chemical mechanical planarization (CMP) process can be applied that, depending on the composition of the terminal, can cause damage that affect operating characteristics of the finished memory device or cell. In some embodiments, such damage can be removed by one or more post-CMP processes. In some embodiments, such damage can be mitigated so as to prevent the damage from occurring at all, by, e.g., forming a sacrificial layer atop the terminal prior to performing the CMP process. Thus, the sacrificial layer can operate to protect the terminal from damage resulting from the CMP process, with the remainder of the sacrificial layer being removed prior to completing the fabrication of the two-terminal memory device.

Abstract: Techniques for processing silicon germanium (SiGe) thin films to reduce surface roughness thereof are provided herein. In an aspect, a method is disclosed that includes depositing a silicon germanium (SiGe) material upon a surface of a substrate at or below about 450 degrees Celsius, the substrate having a plurality of CMOS devices therein and forming, from the deposited SiGe material, a SiGe material film, wherein the SiGe material film has a jagged surface comprising projections and indentations extended along a direction substantially perpendicular to the surface of the substrate. The method further includes performing a chemical mechanical planarization (CMP) process to the jagged surface of the SiGe material, and reducing variations between the projections and the indentions along the direction substantially perpendicular to the surface of the substrate, and transforming the jagged surface of the SiGe material into a relatively smooth surface, compared to the jagged surface.