Abstract: Disclosed are a programmable, random logic device array, and a method of forming such a device. The device comprises a substrate, and a semiconductor layer above the substrate. That semiconductor layer, in turn, includes a first region of a first semiconductor type, an array of spaced apart second regions of a second semiconductor type, and a plurality of space-charge regions. Each of the space charge regions extends around a respective one of the second regions and separates that one of the second regions from the first region of the semiconductor layer. The programmable, random, logic device array further comprises first and second sets of contacts. The first set of contacts are in electrical contact with areas of said first region of the semiconductor layer, and the second set of contacts are in electrical contact with the second regions.

Abstract: The present invention provides a method, system, and program product for the deployment and use of an intelligent sensor network. More particularly, the method, system, and program product of the present invention enable the deployment and use of fused sensors in an arbitrary area or volume. In a first aspect, the invention provides a method for employing a multi-sensor network, the method comprising the steps of employing a first sensor, employing a plurality of additional sensors, a position of each additional sensor within the network being relative in at least two dimensions to only one of the first sensor and an adjacent sensor nearer the first sensor, and employing a routing algorithm for determining a routing path for data in the network.

Abstract: Disclosed are a programmable, random logic device array, and a method of forming such a device. The device comprises a substrate, and a semiconductor layer above the substrate. That semiconductor layer, in turn, includes a first region of a first semiconductor type, an array of spaced apart second regions of a second semiconductor type, and a plurality of space-charge regions. Each of the space charge regions extends around a respective one of the second regions and separates that one of the second regions from the first region of the semiconductor layer. The programmable, random, logic device array further comprises first and second sets of contacts. The first set of contacts are in electrical contact with areas of said first region of the semiconductor layer, and the second set of contacts are in electrical contact with the second regions.

Abstract: A structure for a system of chip packages includes a master substrate and at least one subset substrate of the master substrate. The subset substrate includes a portion of the master substrate that has an identical pin out pattern as the portion of the master substrate. The subset substrate has identical internal net lists as the portion of the master substrate. The subset substrate is adapted to accommodate a smaller chip than the master substrate. The master substrate is the largest substrate in the system. The invention also prepares a system of chip packages. The invention selects a master substrate and then selects a subset substrate of the master substrate.

Abstract: A dielectric substrate having an embedded inductor wherein each turn of the inductor traverses several layers such that the top and bottom of each turn of the inductor are parallel to each other but are in different layers and the sides of each turn of the inductor traverse at least one layer to connect the top and bottom of the inductor.

Abstract: A dielectric substrate having an embedded inductor wherein each turn of the inductor traverses several layers such that the top and bottom of each turn of the inductor are parallel to each other but are in different layers and the sides of each turn of the inductor traverse at least one layer to connect the top and bottom of the inductor.

Abstract: MLC (multilayer ceramic) frequency selective circuit structures are disclosed. The MLC frequency selective circuit structures have a solenoid and toroid coil geometry in a multilayer electronic package which functions as a frequency selective tuned circuit in which both the number of turns and the aspect ratio of the solenoid coil are selected to adjust the tuned frequency. In some embodiments, a plurality of such coils can be connected together to provide a selected bandwidth about a tuned center frequency.

Abstract: MLC (multilayer ceramic) frequency selective circuit structures are disclosed. The MLC frequency selective circuit structures have a solenoid and toroid coil geometry in a multilayer electronic package which functions as a frequency selective tuned circuit in which both the number of turns and the aspect ratio of the solenoid coil are selected to adjust the tuned frequency. In some embodiments, a plurality of such coils can be connected together to provide a selected bandwidth about a tuned center frequency.

Abstract: A dielectric substrate having an embedded inductor wherein each turn of the inductor traverses several layers such that the top and bottom of each turn of the inductor are parallel to each other but are in different layers and the sides of each turn of the inductor traverse at least one layer to connect the top and bottom of the inductor.

Abstract: An apparatus (and method) for testing a DC isolation resistance of a large capacitance network experiencing voltage stress, adds capacitance and resistance to a large resistance network under test, such that the direct current (DC) isolation resistance may be determined without distortion from the alternating current (AC) components of the circuit. The capacitance that is added is determined based on the capacitance of the object, the resistance of the object, and the resistance of the testing apparatus. In one embodiment, because the precise capacitance of the network under test may be unknown, the testing apparatus and method may utilize an additional large capacitor designed to obviate small fluctuations in the capacitance of the network.

Abstract: A method of substrate design of an multilayer ceramic module that uses menu die of the same size is provided. One of these menu die provides a “generic” substrate design having internal wiring with greatest number of input/output (I/O) signal leads of all the dice available. Middle (redistribution) layers include electrical interconnections for both power and the I/O signal lead wires between the dice interface terminals and a bottom surface metallurgy (BSM) layer that has electrical connector pads by use of a customization layer.

Abstract: An apparatus (and method) for testing a DC isolation resistance of a large capacitance network experiencing voltage stress, adds capacitance and resistance to a large resistance network under test, such that the direct current (DC) isolation resistance may be determined without distortion from the alternating current (AC) components of the circuit. The capacitance that is added is determined based on the capacitance of the object, the resistance of the object, and the resistance of the testing apparatus. In one embodiment, because the precise capacitance of the network under test may be unknown, the testing apparatus and method may utilize an additional large capacitor designed to obviate small fluctuations in the capacitance of the network.

Abstract: A method of substrate design of a multilayer ceramic module that uses menu die of the same size. One of these menu die provides a “generic” substrate design having internal wiring with the greatest number of input/output (I/O) signal leads of all the dies available. Middle (redistribution) layers include electrical interconnections for both power and the I/O signal lead wires between the die interface terminals and a bottom surface metallurgy (BSM) layer that has electrical connector pads by use of a customization layer.

Abstract: A thin-layer metallization structure in which the final gold layer is deposited by evaporation with the surface onto which it is evaporated maintained at an elevated temperature. By evaporating the uppermost gold layer of the structure at an elevated substrate temperature, the gold atoms have a higher mobility, causing the deposited gold to spread over the edge of the structure and cover the otherwise exposed edges, including the edge at the copper interface.

Abstract: A direct distribution wiring system is provided which facilitates the effecting of repair or engineering change in a Multi-chip module (MCM) while eliminating the need for redistribution and/or buried connections between IC attachment pads and engineering change pads, thus eliminating the need for patterned conductor layers corresponding to such functions. The operation of the MCM is improved by the wiring system allowing the reduction of lumped capacitances by disconnection of defective conductors, accomplished by providing severable connectors in a direct distribution structure, as well as the elimination of redistribution wiring layers and increased IC density on the MCM. Full potential fault coverage as well as full discretion in reversible engineering changes is provided by forming all elements of the wiring system on the surface of the device.

Abstract: A method is disclosed for fabricating a small area, self aligned guard ring in a Schottky barrier diode. A vertically-walled hole is anisotropically etched completely through a dielectric layer on a silicon substrate. A layer of doped polycrystalline silicon is deposited over the apertured dielectric layer. The polycrystalline silicon is reactively ion etched away to leave only a lining about the perimeter of the hole in the dielectric layer. The structure is heated to diffuse the dopant from the lining into the substrate. Schottky diode metal is deposited on the substrate exposed through the lined aperture in the dielectric layer.

Abstract: A specially designed module and integrated circuit chip therefor which permits the sharing of module EC pads between chip receiver and driver circuits. The chip has a direct normal input line to each receiver circuit therein and a direct normal output line from each driver circuit therein along with signal lines from each of those circuits to various EC pads. The chip further includes a switching and control circuit for switching the receiver circuits and driver circuits between their normal and EC lines to effect an electronic delete function. In a preferred embodiment, a majority of the EC pads are switchably connected via the switching and control circuit to different sets of three adjacent receiver circuits, driver circuits, or a combination thereof. The design permits the use of approximately half the EC pads normally required for a module, while permitting EC connections to be made in most cases to three adjacent receiver or driver circuits simultaneously.

Abstract: A new dotting circuit for integrated circuit chips which provides line switching, as well as simultaneous true and complementary outputs, while eliminating the need for the standard collector circuit voltage clamp. This circuit is implemented by the collector dotting of two or more input transistors, the collector dotting of their respective reference transistors, the emitter dotting of one input transistor and a reference transistor to a constant current source, the emitter dotting of the other input transistor and the other reference transistor to a different constant current source, and an inhibit circuit for permitting current to flow to only one of the emitter-dotted circuits in accordance with a logic control signal.

Abstract: A method and resulting structure for making contact to a narrow width PN junction region in any desired semiconductor body is described. A substantially vertical conformal conductive layer is formed over the desired PN junction region. The body is heated at a suitable temperature to cause a dopant to diffuse from the vertical conductive layer into the semiconductor body to form the narrow width PN junction region. A substantially horizontal conductive layer makes contact to the substantially vertical layer so as to have the horizontal conductive layer in electrical contact to the PN junction region. Electrical contact can be made to the horizontal conductive layer at any convenient location. A lateral PNP transistor is one type of very small device that can be made using the method of the present invention.

Abstract: A method is disclosed for fabricating a small area, self aligned guard ring in a Schottky barrier diode. A vertically-walled hole is anisotropically etched completely through a dielectric layer on a silicon substrate. A layer of doped polycrystalline silicon is deposited over the apertured dielectric layer. The polycrystalline silicon is reactively ion etched away to leave only a lining about the perimeter of the hole in the dielectric layer. The structure is heated to diffuse the dopant from the lining into the substrate. Schottky diode metal is deposited on the substrate exposed through the lined aperture in the dielectric layer.