Patents by Inventor Haruhiko Terada

Haruhiko Terada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10902913
    Abstract: The semiconductor device of the present disclosure includes a plurality of first selection lines provided in a first region, extending in a first direction, and aligned in a second direction; a plurality of second selection lines provided in a second region having a portion that overlaps a portion of the first region, extending in the second direction, and aligned in the first direction; a plurality of third selection lines provided in a third region having a portion that overlaps a portion of the second region, extending in the first direction, and aligned in the second direction; a plurality of fourth selection lines provided in a fourth region having one portion that overlaps a portion of the first region and having another portion that overlaps a portion of the third region, extending in the second direction, and aligned in the first direction; a first coupling part, a first coupling part, a first coupling part, and a first coupling part coupled, respectively, to the plurality of first selection lines, th
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: January 26, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Haruhiko Terada
  • Publication number: 20200286953
    Abstract: In a memory unit according to an embodiment of the present disclosure, a memory cell array is configured, when, of a plurality of memory cells, multiple first memory cells whose corresponding fourth wiring line and first wiring line are different from one another are simultaneously accessed, to allow for simultaneous access to the multiple first memory cells, without allowing for simultaneous access to memory cells corresponding to the fourth wiring line shared by the first memory cells.
    Type: Application
    Filed: March 5, 2018
    Publication date: September 10, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Makoto KITAGAWA, Yoshiyuki SHIBAHARA, Haruhiko TERADA, Yotaro MORI
  • Publication number: 20200273909
    Abstract: Provided is a memory device that has a structure suitable for still higher integration while securing production easiness, and includes n memory cell units stacked, on a substrate, in order as first to n-th memory cell units in a first direction. The n memory cell units each include: one or more first electrodes; a plurality of second electrodes each provided to intersect the first electrode; a plurality of memory cells provided at respective intersections of the first electrode and the second electrodes and each coupled to both the first and second electrodes; and one or more lead lines coupled to the first electrode to form one or more coupling parts, which, in (m+1)-th memory cell unit, are located at a position where the coupling parts and m-th memory cell region surrounded by the memory cells in m-th memory cell unit overlap each other in the first direction.
    Type: Application
    Filed: May 12, 2020
    Publication date: August 27, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Haruhiko TERADA
  • Patent number: 10700130
    Abstract: Provided is a memory device that has a structure suitable for still higher integration while securing production easiness, and includes n memory cell units stacked, on a substrate, in order as first to n-th memory cell units in a first direction. The n memory cell units each include: one or more first electrodes; a plurality of second electrodes each provided to intersect the first electrode; a plurality of memory cells provided at respective intersections of the first electrode and the second electrodes and each coupled to both the first and second electrodes; and one or more lead lines coupled to the first electrode to form one or more coupling parts, which, in (m+1)-th memory cell unit, are located at a position where the coupling parts and m-th memory cell region surrounded by the memory cells in m-th memory cell unit overlap each other in the first direction.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: June 30, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Haruhiko Terada
  • Publication number: 20200202931
    Abstract: The semiconductor device of the present disclosure includes a plurality of first selection lines provided in a first region, extending in a first direction, and aligned in a second direction; a plurality of second selection lines provided in a second region having a portion that overlaps a portion of the first region, extending in the second direction, and aligned in the first direction; a plurality of third selection lines provided in a third region having a portion that overlaps a portion of the second region, extending in the first direction, and aligned in the second direction; a plurality of fourth selection lines provided in a fourth region having one portion that overlaps a portion of the first region and having another portion that overlaps a portion of the third region, extending in the second direction, and aligned in the first direction; a first coupling part, a first coupling part, a first coupling part, and a first coupling part coupled, respectively, to the plurality of first selection lines, th
    Type: Application
    Filed: April 5, 2018
    Publication date: June 25, 2020
    Inventor: HARUHIKO TERADA
  • Publication number: 20200203426
    Abstract: A semiconductor device according to the present disclosure includes: a plurality of first selection lines provided in a region other than a plurality of opening regions in a first region in a first selection line layer, and having a predetermined width, the plurality of first selection lines extending in a first direction and disposed side by side in a second direction, the second direction intersecting with the first direction; a first metal wiring line formed in a layer above the first selection line layer; a first through wiring line penetrating an insulating layer formed on the first selection line layer, and coupling a first line of the plurality of first selection lines and the first metal wiring line to each other; a second through wiring line provided in a first opening region of the plurality of opening regions, and penetrating the first selection line layer, the second through wiring line having one end coupled to the first metal wiring line; a first storage element having a first terminal, and a se
    Type: Application
    Filed: April 17, 2018
    Publication date: June 25, 2020
    Inventor: HARUHIKO TERADA
  • Patent number: 10672472
    Abstract: Provided is an initialization control unit that causes a resistance value of a variable resistive element in an access restriction region to be changed to an initial value larger than a predetermined value. The resistance value is changed in a read only mode among the read only mode in which writing to the access restriction region is prohibited and a writable mode in which the writing to the access restriction region is permitted. The access restriction region is in a memory cell array in which the variable resistive elements are arranged, and the initialization control unit transitions to the writable mode. In addition, a write control unit causes a resistance value of an element corresponding to write data among the variable resistive elements in the access restriction region to be changed to a value smaller than the initial value in the writable mode, and transitions to the read only mode.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: June 2, 2020
    Assignee: Sony Corporation
    Inventor: Haruhiko Terada
  • Patent number: 10664343
    Abstract: To suppress an increase in a voltage drop in a non-volatile memory including a variable resistive element installed therein. A memory controller includes a voltage drop amount estimating unit and an encoding unit. The voltage drop amount estimating unit estimates a voltage drop amount from a wiring resistance of a wiring up to a memory cell and a leakage current occurring in the memory cell when original data is caused to be held in the memory cell. The encoding unit performs a predetermined encoding process on the original data in a case in which the estimated voltage drop amount exceeds a predetermined threshold value.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: May 26, 2020
    Assignee: Sony Corporation
    Inventor: Haruhiko Terada
  • Publication number: 20200098425
    Abstract: A memory apparatus includes a memory cell disposed at an intersection of a first wiring line and a second wiring line, and including a variable resistor and a selector, the variable resistor having a resistance state that changes to a first resistance state and a second resistance state, and a drive circuit that writes data to the memory cell by changing the variable resistor from the first resistance state to the second resistance state, and erases the data stored in the memory cell by changing the variable resistor from the second resistance state to the first resistance state. When erasing the data, the drive circuit changing in a stepwise manner a voltage applied to the memory cell, and changing in a stepwise manner a current limit value that limits a magnitude of a current flowing through the memory cell.
    Type: Application
    Filed: May 11, 2018
    Publication date: March 26, 2020
    Inventors: YOTARO MORI, MAKOTO KITAGAWA, JUN OKUNO, HARUHIKO TERADA
  • Publication number: 20200082881
    Abstract: A storage device according to the present disclosure includes: a first storage section that includes a plurality of first wiring lines, a plurality of second wiring lines, and a plurality of first memory cells, the plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines, the plurality of second wiring lines extending in a second direction and including a plurality of third selection lines and a plurality of fourth selection lines; a first selection line driver that applies a first voltage to one or more selection lines of the plurality of first selection lines and applies a second voltage to one or more selection lines of the plurality of second selection lines, the first voltage being one of a first selection voltage and a second selection voltage, and the second voltage being one of the first selection voltage and the second selection voltage and being different from the first voltage; and a second selection
    Type: Application
    Filed: November 9, 2017
    Publication date: March 12, 2020
    Inventor: HARUHIKO TERADA
  • Publication number: 20200020411
    Abstract: A storage device according to the present disclosure includes: a plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines; a plurality of second wiring lines extending in a second direction and including a plurality of third selection lines and a plurality of fourth selection lines, the second direction intersecting the first direction; a plurality of first memory cells; a first driver including a first selection line driver that drives the plurality of first selection lines on a basis of a first selection control signal and a second selection line driver that drives the plurality of second selection lines on a basis of the first selection control signal, the first and second selection line drivers being arranged side-by-side in the first direction; and a second driver including a third selection line driver that drives the plurality of third selection lines on a basis of a second selection control signal and a
    Type: Application
    Filed: March 13, 2018
    Publication date: January 16, 2020
    Inventors: HARUHIKO TERADA, MAKOTO KITAGAWA, YOSHIYUKI SHIBAHARA, YOTARO MORI
  • Publication number: 20190259811
    Abstract: Provided is a memory device that has a structure suitable for still higher integration while securing production easiness, and includes n memory cell units stacked, on a substrate, in order as first to n-th memory cell units in a first direction. The n memory cell units each include: one or more first electrodes; a plurality of second electrodes each provided to intersect the first electrode; a plurality of memory cells provided at respective intersections of the first electrode and the second electrodes and each coupled to both the first and second electrodes; and one or more lead lines coupled to the first electrode to form one or more coupling parts, which, in (m+1)-th memory cell unit, are located at a position where the coupling parts and m-th memory cell region surrounded by the memory cells in m-th memory cell unit overlap each other in the first direction.
    Type: Application
    Filed: May 3, 2019
    Publication date: August 22, 2019
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Haruhiko TERADA
  • Patent number: 10338984
    Abstract: Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: July 2, 2019
    Assignee: SONY CORPORATION
    Inventors: Yasushi Fujinami, Kenichi Nakanishi, Tsunenori Shiimoto, Tetsuya Yamamoto, Tatsuo Shinbashi, Hideaki Okubo, Haruhiko Terada, Ken Ishii, Hiroyuki Iwaki, Matatoshi Honjo
  • Patent number: 10319787
    Abstract: Provided is a memory device that has a structure suitable for still higher integration while securing production easiness, and includes n memory cell units stacked, on a substrate, in order as first to n-th memory cell units in a first direction. The n memory cell units each include: one or more first electrodes; a plurality of second electrodes each provided to intersect the first electrode; a plurality of memory cells provided at respective intersections of the first electrode and the second electrodes and each coupled to both the first and second electrodes; and one or more lead lines coupled to the first electrode to form one or more coupling parts, which, in (m+1)-th memory cell unit, are located at a position where the coupling parts and m-th memory cell region surrounded by the memory cells in m-th memory cell unit overlap each other in the first direction.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: June 11, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Haruhiko Terada
  • Patent number: 10304528
    Abstract: A memory device of one embodiment of the technology includes: a plurality of memory cells in a matrix arrangement; a plurality of row wirings each coupled to one end of each memory cell; a plurality of column wirings each coupled to another end of each memory cell, a first decoder circuit coupled to each of the row wirings of even-numbered rows; a second decoder circuit coupled to each of the row wirings of odd-numbered rows; a third decoder circuit coupled to each of the column wirings of even-numbered columns; and a fourth decoder circuit coupled to each of the column wirings of odd-numbered columns. The first decoder circuit, the second decoder circuit, the third decoder circuit, and the fourth decoder circuit are constituted by independent circuits from one another.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: May 28, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Haruhiko Terada, Yotaro Mori, Makoto Kitagawa
  • Patent number: 10199102
    Abstract: Delay overhead in a memory device is eliminated. A command accepting unit accepts a read command requesting data reading from the memory device. A control unit selects, in accordance with a state of the memory device, one of a first mode in which a read request, requesting data reading from a memory cell array of the memory device and output of the read data, is issued to the memory device after completion of a preceding request and a second mode in which a sense request requesting data reading from the memory cell array is issued and then a data-out request requesting output of the data read by the sense request is issued to the memory device after a lapse of predetermined time from completion of the preceding request. A request issuing unit issues a request to the memory device in accordance with the first or the second mode selected by the control unit.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: February 5, 2019
    Assignee: Sony Corporation
    Inventor: Haruhiko Terada
  • Publication number: 20190035460
    Abstract: To suppress the fluctuation of the voltage drop in the non-volatile memories including the variable resistive element installed therein. An initialization control unit causes a resistance value of a variable resistive element in an access restriction region to be changed to an initial value larger than a predetermined value in a read only mode among the read only mode in which writing to the access restriction region in a memory cell array in which the variable resistive elements are arranged is prohibited and a writable mode in which the writing to the access restriction region is permitted, and transitions to the writable mode. In addition, a write control unit causes a resistance value of an element corresponding to write data among the variable resistive elements in the access restriction region to be changed to a value smaller than the initial value in the writable mode, and transitions to the read only mode.
    Type: Application
    Filed: December 1, 2016
    Publication date: January 31, 2019
    Applicant: Sony Corporation
    Inventor: Haruhiko TERADA
  • Publication number: 20190034266
    Abstract: To suppress an increase in a voltage drop in a non-volatile memory including a variable resistive element installed therein. A memory controller includes a voltage drop amount estimating unit and an encoding unit. The voltage drop amount estimating unit estimates a voltage drop amount from a wiring resistance of a wiring up to a memory cell and a leakage current occurring in the memory cell when original data is caused to be held in the memory cell. The encoding unit performs a predetermined encoding process on the original data in a case in which the estimated voltage drop amount exceeds a predetermined threshold value.
    Type: Application
    Filed: December 1, 2016
    Publication date: January 31, 2019
    Applicant: Sony Corporation
    Inventor: Haruhiko TERADA
  • Patent number: 10115669
    Abstract: In a memory cell unit array, memory cell units each constituted of first wires, second wires, and a nonvolatile memory cell are arranged in a two-dimensional matrix form in a first direction and a second direction. Each of the memory cell units includes a control circuit below it. The control circuit is constituted of a first control circuit and a second control circuit. The second wires are connected to the second control circuit. Some of the first wires that constitute the memory cell unit are connected to the first control circuit that constitutes this memory cell unit. Others of the first wires are connected to the first control circuit that constitutes an adjacent memory cell unit adjacent thereto in the first direction.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: October 30, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Haruhiko Terada, Makoto Kitagawa
  • Publication number: 20180293025
    Abstract: To enable data to be transferred between a memory and a memory controller with accuracy. A memory-side interface circuit synchronizes a first periodic signal having a greater number of cycles than a number of pieces of unit data obtained by dividing read data read from a memory cell by a predetermined unit with the unit data and to sequentially transmit the first periodic signal and the unit data. A controller-side interface circuit sequentially holds the transmitted unit data in holding units of a plurality of stages in synchronization with the periodic signal and sequentially reads and outputs the held unit data in synchronization with a second periodic signal.
    Type: Application
    Filed: October 8, 2015
    Publication date: October 11, 2018
    Inventors: Lui SAKAI, Yoshiyuki SHIBAHARA, Tetsuo YOSHIDA, Hidenobu KAKIOKA, Haruhiko TERADA