Abstract: The present disclosure relates to a distance measuring device, a distance measuring method, and a program capable of achieving LiDAR with high accuracy at low cost. In a plurality of division times obtained by dividing a modulation cycle for chirp-modulating frequencies of transmission beams of a plurality of channels, light emission and extinction of a plurality of light sources are controlled in a unique pattern for each light source, an interference beam between a reception beam and a transmission beam is detected, digitized into a reception signal sequence, and subjected to FFT to obtain a frequency spectrum, a beat frequency is specified from comparison of magnitude of peaks, and a distance to a measurement target and a relative speed are measured. The present disclosure can be applied to LiDAR.

Abstract: To effectively use a memory when a plurality of memories is combined to constitute a memory module. A memory access control unit performs writing by dividing write data and an error correction code thereof into a plurality of memories, and acquires presence or absence of occurrence of a verify error in each of the plurality of memories related to the writing. In a case where the verify errors occur in at least any of the plurality of memories, an error bit length acquisition unit acquires bit lengths of the verify errors from the plurality of memories.

Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a first memory cell layer including a first selection line extending in a first direction, a second selection line extending in a second direction, and a first memory cell coupled to the first selection line and the second selection line, a second memory cell layer provided above the first memory cell layer, and including a third selection line extending in the first direction, a fourth selection line extending in the second direction, and a second memory cell coupled to the third selection line and the fourth selection line; and a first wiring layer provided between the first memory cell layer and the second memory cell layer and including a first metal wiring line.

Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a memory cell array including a plurality of first selection lines extending in a first direction, a plurality of second selection lines extending in a second direction, and a plurality of memory cells each provided between the plurality of first selection lines and the plurality of second selection lines; a voltage generator that is configured to generate a selection voltage to be applied to one of the plurality of first selection lines; and a decoder section that includes a plurality of selection transistors and a gate driving section, and selects one of the plurality of first selection lines and applies the selection voltage to the selected first selection line, the plurality of selection transistors each provided in a plurality of selection paths coupling the plurality of first selection lines and the voltage generator, the gate driving section that drives gates of the plurality of transistors and is configured to apply

Abstract: In a memory module according to an embodiment of the present disclosure, a controller, upon reception of a read command including a logical address, converts the logical address included in the read command into a physical address using address lookup information. The controller further inputs a first physical address, which is a portion of the physical address obtained by the conversion, to a non-volatile memory via a first address bus terminal, and then inputs a second physical address, which is a rest of the physical address obtained by the conversion, to the non-volatile memory via a second address bus terminal, to thereby read data corresponding to the physical address obtained by the conversion from the non-volatile memory.

Abstract: An object is to reduce write failures by eliminating localization of wearout of cells in a memory in accordance with characteristics of a Xp-ReRAM and maximize a lifetime of the memory. The present technology includes a controller that controls an operation of a semiconductor storage device including a writable nonvolatile memory. The controller includes: an access control unit that controls access to data storage regions based on some of a plurality of memory cells in the nonvolatile memory in accordance with an address translation table holding mapping information that indicates a correspondence between physical addresses specifying the data storage regions and logical addresses; and a wear-leveling processor that performs a wear-leveling process that levels wearout of the plurality of memory cells that is caused by the access. The wear-leveling processor performing the wear-leveling process with a predetermined probability at each time of the access.

Abstract: An object of the present disclosure is to provide a memory chip and a method of controlling a memory chip that make it possible to detect a disturb failure. The memory chip includes: a memory cell including a variable resistor element and a switching element, the variable resistor element reversibly changeable between a low resistive state and a high resistive state, and the switching element having nonlinear current-voltage characteristics and being coupled in series to the variable resistor element; a voltage generator that generates a first voltage to be applied to the memory cell in a case where the variable resistor element is changed to the low resistive state, a second voltage to be applied to the memory cell in a case where a resistive state of the variable resistor element is detected, and a specific voltage that is equal to or higher than a half of the first voltage and lower than the second voltage; and a control unit that controls the memory cell.

Abstract: Handling memory cell errors in accordance with error type is disclosed. In one example, a semiconductor storage device includes a nonvolatile memory and a controller that controls access to a storage region of the nonvolatile memory. The controller includes a first error correction processor that performs a first error correction process on a first memory cell group in the storage region on the basis of an ECC, and a second error correction processor that performs a second error correction process on a second memory cell group in the storage region on the basis of an ECP and a patch. The first error correction processor performs the error correction when the first memory cell group has first or second failure types, and the second error correction processor performs the error correction when the second memory cell group has first, second or third failure types.

Abstract: Parallelism of memory access is improved without sacrificing operation margin. A storage unit includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction, and a plurality of memory cells each being inserted at a position at which any one of the plurality of first lines intersects any one of the plurality of second lines. A first driving unit supplies a first voltage having either a positive or a negative polarity to each of the plurality of first lines. A second driving unit supplies a second voltage having a polarity different from the first voltage to one of the plurality of second lines intersecting the plurality of first lines and supplies either a zero potential or a voltage having the same polarity as the first voltage to the remaining second lines intersecting the plurality of first lines.

Abstract: A storage device that avoids unauthorized access attributable to a snapback when simultaneously accessing a plurality of memory cells includes a plurality of first wires extending in a first direction, a plurality of second wires extending in a second direction, and a plurality of memory cells at a position where any of the plurality of first wires and any of the plurality of second wires intersect each other. A first driving unit supplies a first voltage having any of a positive polarity and a negative polarity or a zero potential to each of the plurality of first wires. A second driving unit supplies a second voltage with a different polarity from the first voltage to any one of the plurality of second wires intersecting a first wire to which the first voltage is supplied and supplies a zero potential to a remainder of the plurality of second wires.

Abstract: In a circuit that selects a memory cell and applies a predetermined voltage to two ends of the memory cell, a withstand voltage and a maximum amplitude of a gate voltage are reduced. A memory control circuit includes a plurality of stages of memory decoders configured to select a specific cell of a memory according to a specified address and apply a predetermined voltage to two ends of the specific cell. At least one of the plurality of stages of the memory decoders includes the following four transistors. A first transistor and a second transistor are each provided according to a value to be written to the specific cell. A third transistor and a fourth transistor are provided to bring the specific cell into a non-selected state.

Abstract: A selector malfunction caused by a drift is prevented in a memory having a cross-point structure. A memory cell array is provided with a data area and a drift reference cell. An accumulated drift amount acquisition unit acquires an accumulated drift amount of the drift reference cell. A total drift amount reading unit reads a total drift amount stored in the data area. A refresh control unit adds the accumulated drift amount to the total drift amount to update the total drift amount as a new total drift amount. Further, the refresh control unit refreshes the data area of the memory cell array in a case where the new total drift amount exceeds a predetermined threshold value.

Abstract: Reliability of stored data is improved without increasing power consumption in a case where a threshold of a control element in a memory cell changes. In a memory including the memory cell, a reference cell, and an access control unit, the memory cell changes from a non-conduction state to a conduction state according to an applied voltage at a threshold voltage and changes to a high resistance state and a low resistance state according to the voltage applied in the conduction state. The reference cell changes from a non-conduction state to a conduction state at a reference threshold voltage according to an applied voltage. The access control unit estimates that the reference threshold voltage measured in the reference cell is the threshold voltage of the memory cell and applies a voltage to the memory cell when accessing the memory cell.

Abstract: A semiconductor device includes a plurality of first selection lines extending in a first direction and disposed side by side in a second direction, the second direction intersecting with the first direction, a first metal wiring line formed in a layer above the first selection line layer, a first through wiring line penetrating an insulating layer formed on the first selection line layer, and coupling a first line of the plurality of first selection lines and the first metal wiring line to each other, a second through wiring line penetrating the first selection line layer, the second through wiring line having one end coupled to the first metal wiring line, a first storage element having a first terminal, and a second terminal coupled to the first line, and a first drive circuit coupled to another end of the second through wiring line, and drives the plurality of first selection lines.

Abstract: Provided is a memory device that has a structure suitable for still higher integration while securing production easiness, and includes n memory cell units stacked, on a substrate, in order as first to n-th memory cell units in a first direction. The n memory cell units each include: one or more first electrodes; a plurality of second electrodes each provided to intersect the first electrode; a plurality of memory cells provided at respective intersections of the first electrode and the second electrodes and each coupled to both the first and second electrodes; and one or more lead lines coupled to the first electrode to form one or more coupling parts, which, in (m+1)-th memory cell unit, are located at a position where the coupling parts and m-th memory cell region surrounded by the memory cells in m-th memory cell unit overlap each other in the first direction.

Abstract: A memory apparatus includes a memory cell disposed at an intersection of a first wiring line and a second wiring line, and including a variable resistor and a selector, the variable resistor having a resistance state that changes to a first resistance state and a second resistance state, and a drive circuit that writes data to the memory cell by changing the variable resistor from the first resistance state to the second resistance state, and erases the data stored in the memory cell by changing the variable resistor from the second resistance state to the first resistance state. When erasing the data, the drive circuit changing in a stepwise manner a voltage applied to the memory cell, and changing in a stepwise manner a current limit value that limits a magnitude of a current flowing through the memory cell.

Abstract: In a memory unit according to an embodiment of the present disclosure, a memory cell array is configured, when, of a plurality of memory cells, multiple first memory cells whose corresponding fourth wiring line and first wiring line are different from one another are simultaneously accessed, to allow for simultaneous access to the multiple first memory cells, without allowing for simultaneous access to memory cells corresponding to the fourth wiring line shared by the first memory cells.

Abstract: A storage device according to the present disclosure includes: a plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines; a plurality of second wiring lines extending in a second direction and including a plurality of third selection lines and a plurality of fourth selection lines, the second direction intersecting the first direction; a plurality of first memory cells; a first driver including a first selection line driver that drives the plurality of first selection lines on a basis of a first selection control signal and a second selection line driver that drives the plurality of second selection lines on a basis of the first selection control signal, the first and second selection line drivers being arranged side-by-side in the first direction; and a second driver including a third selection line driver that drives the plurality of third selection lines on a basis of a second selection control signal and a

Abstract: Provided is a storage device that includes a plurality of first wiring lines including a plurality of first and second selection lines, a plurality of second wiring lines including a plurality of third and fourth selection lines, a first selection line driver that applies a first voltage and a second voltage to one or more selection lines of the plurality of first and second selection lines respectively, the first voltage and the second voltage being one of a first and a second selection voltage, and the first and the second voltage are different, and a second selection line driver that applies a third voltage and a fourth voltage to one or more selection lines of the plurality of third and fourth selection lines respectively, the third voltage and the fourth voltage being one of the first and the second selection voltage, and the third and the fourth voltage being different.

Abstract: The semiconductor device of the present disclosure includes a plurality of first selection lines provided in a first region, extending in a first direction, and aligned in a second direction; a plurality of second selection lines provided in a second region having a portion that overlaps a portion of the first region, extending in the second direction, and aligned in the first direction; a plurality of third selection lines provided in a third region having a portion that overlaps a portion of the second region, extending in the first direction, and aligned in the second direction; a plurality of fourth selection lines provided in a fourth region having one portion that overlaps a portion of the first region and having another portion that overlaps a portion of the third region, extending in the second direction, and aligned in the first direction; a first coupling part, a first coupling part, a first coupling part, and a first coupling part coupled, respectively, to the plurality of first selection lines, th