Abstract: To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error in the read data and specifies memory cells in which the error is present among the plurality of memory cells. A re-read processing unit performs a re-read process for reading data, as re-read data, from the specified memory cells on the basis of a second threshold different from the first threshold. A refresh processing unit rewrites, for a memory cell of which the re-read data has a different value from the read data among the specified memory cells, data with the re-read data as a refresh process.

Abstract: Delay overhead in a memory device is eliminated. A command accepting unit accepts a read command requesting data reading from the memory device. A control unit selects, in accordance with a state of the memory device, one of a first mode in which a read request, requesting data reading from a memory cell array of the memory device and output of the read data, is issued to the memory device after completion of a preceding request and a second mode in which a sense request requesting data reading from the memory cell array is issued and then a data-out request requesting output of the data read by the sense request is issued to the memory device after a lapse of predetermined time from completion of the preceding request. A request issuing unit issues a request to the memory device in accordance with the first or the second mode selected by the control unit.

Abstract: Provided is a memory device that has a structure suitable for still higher integration while securing production easiness, and includes n memory cell units stacked, on a substrate, in order as first to n-th memory cell units in a first direction. The n memory cell units each include: one or more first electrodes; a plurality of second electrodes each provided to intersect the first electrode; a plurality of memory cells provided at respective intersections of the first electrode and the second electrodes and each coupled to both the first and second electrodes; and one or more lead lines coupled to the first electrode to form one or more coupling parts, which, in (m+1)-th memory cell unit, are located at a position where the coupling parts and m-th memory cell region surrounded by the memory cells in m-th memory cell unit overlap each other in the first direction.

Abstract: A memory device of one embodiment of the technology includes: a plurality of memory cells in a matrix arrangement; a plurality of row wirings each coupled to one end of each memory cell; a plurality of column wirings each coupled to another end of each memory cell, a first decoder circuit coupled to each of the row wirings of even-numbered rows; a second decoder circuit coupled to each of the row wirings of odd-numbered rows; a third decoder circuit coupled to each of the column wirings of even-numbered columns; and a fourth decoder circuit coupled to each of the column wirings of odd-numbered columns. The first decoder circuit, the second decoder circuit, the third decoder circuit, and the fourth decoder circuit are constituted by independent circuits from one another.

Abstract: A storage control device includes: a detection unit that determines whether a preliminary process of saving data from a first memory to a second memory is necessary, where the second memory includes a suspend area and a typical area; a preliminary processing unit that writes a first value to the suspend area when the detection unit has determined that the preliminary process is necessary; and a saving processing unit that writes a second value corresponding to the data. The first value is different from the second value when the detection unit has determined that the preliminary process is necessary.

Abstract: To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error in the read data and specifies memory cells in which the error is present among the plurality of memory cells. A re-read processing unit performs a re-read process for reading data, as re-read data, from the specified memory cells on the basis of a second threshold different from the first threshold. A refresh processing unit rewrites, for a memory cell of which the re-read data has a different value from the read data among the specified memory cells, data with the re-read data as a refresh process.

Abstract: In a memory cell unit array, memory cell units each constituted of first wires, second wires, and a nonvolatile memory cell are arranged in a two-dimensional matrix form in a first direction and a second direction. Each of the memory cell units includes a control circuit below it. The control circuit is constituted of a first control circuit and a second control circuit. The second wires are connected to the second control circuit. Some of the first wires that constitute the memory cell unit are connected to the first control circuit that constitutes this memory cell unit. Others of the first wires are connected to the first control circuit that constitutes an adjacent memory cell unit adjacent thereto in the first direction.

Abstract: Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.

Abstract: When reading and writing are successively performed at the same address, the access to the storage area is streamlined. A memory reading unit reads data stored at a predetermined address in a memory array, and stores the data read from the memory array into a read data holding unit, the data read from the memory array being stored as read data. A read data outputting unit outputs the read data stored in the read data holding unit to a requester. A memory writing unit performs writing at a write target address in the memory array in accordance with the write data to be written into the memory array and the read data. A control unit controls the memory writing unit to operate only when the write target address matches the address of the read data.

Abstract: A memory includes a buffer which retains data, a band conversion unit converts a band of an internal data bus that is used for data transfer between the band conversion unit and the buffer which retains data into a band wider than that of an external data bus that is used for data transfer between the band conversion unit and a memory controller, and an access control unit controls access to a memory cell using the buffer, during a wait time occurring in the internal data bus due to a difference between the band of the internal data bus and the band of the external data bus.

Abstract: A memory control apparatus includes a temperature obtaining unit, a priority determination unit, and a write processing unit. The temperature obtaining unit is configured to obtain, in a memory having a plurality of measurement areas each including a plurality of unit areas, temperatures measured in the plurality of measurement areas. The priority determination unit is configured to determine a priority for each unit area in accordance with a degree of consumption and the temperature of the measurement area including the unit areas, the degree of consumption being a degree of consumption of the unit area which is caused by a write process performed. The write processing unit is configured to preferentially perform the write process with respect to the unit area having a higher priority as a data write destination.

Abstract: Disclosed herein is an oscillation circuit including: a control transistor changing an electric potential at an output terminal thereof by proceeding to one of a conduction state and a non-conduction state in accordance with an electric potential at an input terminal thereof; a transistor as an object of a measurement having a polarity of a channel identical to that of the control transistor, and connected in series with the control transistor between a power source and a ground; a capacitor delaying the change in the electric potential at the output terminal in accordance with a value of a leakage current leaked from the transistor as an object of a measurement when the control transistor proceeds from the conduction state to the non-conduction state; and an inversion circuit inverting the electric potential at the output terminal, thereby feeding the inverted electric potential back to the input terminal.

Abstract: A memory includes a buffer which retains data, a band conversion unit converts a band of an internal data bus that is used for data transfer between the band conversion unit and the buffer which retains data into a band wider than that of an external data bus that is used for data transfer between the band conversion unit and a memory controller, and an access control unit controls access to a memory cell using the buffer, during a wait time occurring in the internal data bus due to a difference between the band of the internal data bus and the band of the external data bus.

Abstract: A storage control device includes: a detection unit that determines whether a preliminary process of saving data from a first memory to a second memory is necessary, where the second memory includes a suspend area and a typical area; a preliminary processing unit that writes a first value to the suspend area when the detection unit has determined that the preliminary process is necessary; and a saving processing unit that writes a second value corresponding to the data. The first value is different from the second value when the detection unit has determined that the preliminary process is necessary.

Abstract: A memory control apparatus includes a temperature obtaining unit, a priority determination unit, and a write processing unit. The temperature obtaining unit is configured to obtain, in a memory having a plurality of measurement areas each including a plurality of unit areas, temperatures measured in the plurality of measurement areas. The priority determination unit is configured to determine a priority for each unit area in accordance with a degree of consumption and the temperature of the measurement area including the unit areas, the degree of consumption being a degree of consumption of the unit area which is caused by a write process performed. The write processing unit is configured to preferentially perform the write process with respect to the unit area having a higher priority as a data write destination.

Abstract: A system for charge processing tolls and the like. A vehicle mounted device detects the position of a vehicle 32 using GPS, and transmits position information via a wireless channel to a central station. The central station performs charge processing (calculation) for an area in which a charge is applied based on the position of the vehicle, and transmits the charge to the vehicle mounted device. The vehicle mounted device collects a toll from a prepaid card or IC card or the like on the basis of the received charge processing result.

Abstract: A toll collection arrangement based on the position and travel of a vehicle. A charging area is defined with a buffer area surrounding it. Charges are made when a vehicle enters the charging area for the first time from the buffer area. Later excursions from the charging area into the buffer area and returns from the buffer area to the charging area are not double charged. Vehicle position information can be GPS based.

Abstract: The present invention provides for a device which detects positional information of a moving vehicle. That information is then used to determine whether the moving vehicle is preparing to enter an area where a charge is applied. If a charge is to be applied, the device notifies those inside and outside the moving vehicle of the processing state of the charge processing. The present invention provides for a multitude of notification means. In addition, the present invention provides for a device which is able to collect many different types of information while detecting position and charge information.

Abstract: A charging system which carries out position confirmation of a moving body at a place where there is a radio wave blocked facility, and which carries out automatic detection of GPS antenna blockage for avoiding charging. The charging system includes a GPS positioning device for recognizing a vehicle position, a vehicle speed pulse measuring device for dead reckoning navigating, a monitor device which generates information expressing a current position by using these, and a charging processing which judges whether or not a recognized current position is within a charge area and which carries out data processing for charging. The monitor includes a simple map database which includes positions of facilities or geographical features at which GPS positioning is impossible, and when GPS positioning is impossible, the facility or geographical feature corresponding to the current position is detected, and that position is made to be a current position.

Abstract: A charge applicable area Z is formed from a core area 50 and a buffer area 52 whose width r is set in accordance with the amount of error in the position recognition of a GPS in order that a charge is only applied to a vehicle that has entered a charge applicable area Z and that no charge is applied to a vehicle outside this area. As a result, when a vehicle is located outside the charge applicable area, although the recognized position existence probability circle 54 used in the GPS position detection may overlap with the buffer area 52, it does not go as far as the core area 50. Accordingly, even if the vehicle is recognized as being in the buffer area 52, it is possible that the vehicle is not actually located inside the charge applicable area, therefore no specifying that the vehicle is located inside the charge applicable area is authorized.