Patents by Inventor Haruka SAKUMA
Haruka SAKUMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11665908Abstract: A semiconductor memory device comprises: a substrate; a first semiconductor portion provided separated from the substrate in a first direction intersecting a surface of the substrate, the first semiconductor portion extending in a second direction intersecting the first direction; a first gate electrode extending in the first direction; a first insulating portion which is provided between the first semiconductor portion and the first gate electrode, includes hafnium (Hf) and oxygen (O), and includes an orthorhombic crystal as a crystal structure; a first conductive portion provided between the first semiconductor portion and the first insulating portion; and a second insulating portion provided between the first semiconductor portion and the first conductive portion. An area of a facing surface of the first conductive portion facing the first semiconductor portion is larger than an area of a facing surface of the first conductive portion facing the first gate electrode.Type: GrantFiled: September 22, 2020Date of Patent: May 30, 2023Assignee: Kioxia CorporationInventors: Haruka Sakuma, Hidenori Miyagawa, Shosuke Fujii, Kiwamu Sakuma, Fumitaka Arai, Kunifumi Suzuki
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Patent number: 11430500Abstract: A semiconductor storage device includes a plurality of gate electrodes, a semiconductor layer facing the plurality of gate electrodes, a gate insulating layer arranged between each of the plurality of gate electrodes and the semiconductor layer. The gate insulating layer contains oxygen (O) and hafnium (Hf) and has an orthorhombic crystal structure. A plurality of first wirings is connected to the respective gate electrodes. A controller is configured to execute a write sequence and an erasing sequence by applying certain voltages to at least one of the first wirings. The controller is further configured to increase either a program voltage to be applied to the first wirings in the write sequence or an application time of the program voltage in the write sequence after a total number of executions of the write sequence or the erasing sequence has reached a particular number.Type: GrantFiled: March 1, 2021Date of Patent: August 30, 2022Assignee: KIOXIA CORPORATIONInventors: Haruka Sakuma, Kiwamu Sakuma, Masumi Saitoh
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Publication number: 20220093149Abstract: A semiconductor storage device includes a plurality of gate electrodes, a semiconductor layer facing the plurality of gate electrodes, a gate insulating layer arranged between each of the plurality of gate electrodes and the semiconductor layer. The gate insulating layer contains oxygen (O) and hafnium (Hf) and has an orthorhombic crystal structure. A plurality of first wirings is connected to the respective gate electrodes. A controller is configured to execute a write sequence and an erasing sequence by applying certain voltages to at least one of the first wirings. The controller is further configured to increase either a program voltage to be applied to the first wirings in the write sequence or an application time of the program voltage in the write sequence after a total number of executions of the write sequence or the erasing sequence has reached a particular number.Type: ApplicationFiled: March 1, 2021Publication date: March 24, 2022Inventors: Haruka SAKUMA, Kiwamu SAKUMA, Masumi SAITOH
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Publication number: 20210013229Abstract: A semiconductor memory device comprises: a substrate; a first semiconductor portion provided separated from the substrate in a first direction intersecting a surface of the substrate, the first semiconductor portion extending in a second direction intersecting the first direction; a first gate electrode extending in the first direction; a first insulating portion which is provided between the first semiconductor portion and the first gate electrode, includes hafnium (Hf) and oxygen (O), and includes an orthorhombic crystal as a crystal structure; a first conductive portion provided between the first semiconductor portion and the first insulating portion; and a second insulating portion provided between the first semiconductor portion and the first conductive portion. An area of a facing surface of the first conductive portion facing the first semiconductor portion is larger than an area of a facing surface of the first conductive portion facing the first gate electrode.Type: ApplicationFiled: September 22, 2020Publication date: January 14, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Haruka SAKUMA, Hidenori MIYAGAWA, Shosuke FUJI, Kiwamu SAKUMA, Fumitaka ARAI, Kunifumi SUZUKI
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Patent number: 10833103Abstract: A semiconductor memory device includes: a substrate; a plurality of first semiconductor portions arranged in a first direction intersecting a surface of the substrate; a first gate electrode extending in the first direction, the first gate electrode facing the plurality of first semiconductor portions from a second direction intersecting the first direction; a first insulating portion provided between the first semiconductor portions and the first gate electrode; a first wiring separated from the first gate electrode in the first direction; a second semiconductor portion connected to one end in the first direction of the first gate electrode and to the first wiring; a second gate electrode facing the second semiconductor portion; and a second insulating portion provided between the second semiconductor portion and the second gate electrode.Type: GrantFiled: September 6, 2019Date of Patent: November 10, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Haruka Sakuma, Hidenori Miyagawa, Shosuke Fujii, Kiwamu Sakuma, Fumitaka Arai
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Publication number: 20200303418Abstract: A semiconductor memory device includes: a substrate; a plurality of first semiconductor portions arranged in a first direction intersecting a surface of the substrate; a first gate electrode extending in the first direction, the first gate electrode facing the plurality of first semiconductor portions from a second direction intersecting the first direction; a first insulating portion provided between the first semiconductor portions and the first gate electrode; a first wiring separated from the first gate electrode in the first direction; a second semiconductor portion connected to one end in the first direction of the first gate electrode and to the first wiring; a second gate electrode facing the second semiconductor portion; and a second insulating portion provided between the second semiconductor portion and the second gate electrode.Type: ApplicationFiled: September 6, 2019Publication date: September 24, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Haruka SAKUMA, Hidenori Miyagawa, Shosuke Fujii, Kiwamu Sakuma, Fumitaka Arai
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Patent number: 10446552Abstract: According to one embodiment, a memory element includes a first conductive layer, a second conductive layer, and a first layer. The first conductive layer includes an ion source. The first layer includes a first element and is provided between the first conductive layer and the second conductive layer. An electronegativity of the first element is greater than 2. The first layer includes a first region and a second region. The first region includes the first element. The second region is provided between the first region and the second conductive layer. The second region does not include the first element, or the second region includes the first element, and a concentration of the first element in the first region is higher than a concentration of the first element in the second region.Type: GrantFiled: March 6, 2018Date of Patent: October 15, 2019Assignee: Toshiba Memory CorporationInventors: Dandan Zhao, Reika Ichihara, Haruka Sakuma, Yuuichiro Mitani
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Publication number: 20190088655Abstract: According to one embodiment, a memory element includes a first conductive layer, a second conductive layer, and a first layer. The first conductive layer includes an ion source. The first layer includes a first element and is provided between the first conductive layer and the second conductive layer. An electronegativity of the first element is greater than 2. The first layer includes a first region and a second region. The first region includes the first element. The second region is provided between the first region and the second conductive layer. The second region does not include the first element, or the second region includes the first element, and a concentration of the first element in the first region is higher than a concentration of the first element in the second region.Type: ApplicationFiled: March 6, 2018Publication date: March 21, 2019Applicant: Toshiba Memory CorporationInventors: Dandan ZHAO, Reika ICHIHARA, Haruka SAKUMA, Yuuichiro MITANI
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Patent number: 10008509Abstract: Stack structures are arranged in a first direction horizontal to a semiconductor substrate, one of which has a longitudinal direction along a second direction. One stack structure has a plurality of semiconductor layers stacked between interlayer insulating layers. A memory film is formed on side surfaces of the stack structures and include a charge accumulation film of the memory cell. Conductive films are formed on side surfaces of the stack structures via the memory film. One stack structure has a shape increasing in width from above to below in a cross-section including the first and third directions. One conductive film has a shape increasing in width from above to below in a cross-section including the second and third directions. Predetermined portions in the semiconductor layers have different impurity concentrations between upper and lower semiconductor layers.Type: GrantFiled: July 12, 2017Date of Patent: June 26, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Haruka Sakuma, Kiwamu Sakuma, Masahiro Kiyotoshi
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Publication number: 20170309633Abstract: Stack structures are arranged in a first direction horizontal to a semiconductor substrate, one of which has a longitudinal direction along a second direction. One stack structure has a plurality of semiconductor layers stacked between interlayer insulating layers. A memory film is formed on side surfaces of the stack structures and include a charge accumulation film of the memory cell. Conductive films are formed on side surfaces of the stack structures via the memory film. One stack structure has a shape increasing in width from above to below in a cross-section including the first and third directions. One conductive film has a shape increasing in width from above to below in a cross-section including the second and third directions. Predetermined portions in the semiconductor layers have different impurity concentrations between upper and lower semiconductor layers.Type: ApplicationFiled: July 12, 2017Publication date: October 26, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Haruka SAKUMA, Kiwamu Sakuma, Masahiro Kiyotoshi
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Patent number: 9711518Abstract: Stack structures are arranged in a first direction horizontal to a semiconductor substrate, one of which has a longitudinal direction along a second direction. One stack structure has a plurality of semiconductor layers stacked between interlayer insulating layers. A memory film is formed on side surfaces of the stack structures and include a charge accumulation film of the memory cell. Conductive films are formed on side surfaces of the stack structures via the memory film. One stack structure has a shape increasing in width from above to below in a cross-section including the first and third directions. One conductive film has a shape increasing in width from above to below in a cross-section including the second and third directions. Predetermined portions in the semiconductor layers have different impurity concentrations between upper and lower semiconductor layers.Type: GrantFiled: February 11, 2016Date of Patent: July 18, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Haruka Sakuma, Kiwamu Sakuma, Masahiro Kiyotoshi
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Publication number: 20160163719Abstract: Stack structures are arranged in a first direction horizontal to a semiconductor substrate, one of which has a longitudinal direction along a second direction. One stack structure has a plurality of semiconductor layers stacked between interlayer insulating layers. A memory film is formed on side surfaces of the stack structures and include a charge accumulation film of the memory cell. Conductive films are formed on side surfaces of the stack structures via the memory film. One stack structure has a shape increasing in width from above to below in a cross-section including the first and third directions. One conductive film has a shape increasing in width from above to below in a cross-section including the second and third directions. Predetermined portions in the semiconductor layers have different impurity concentrations between upper and lower semiconductor layers.Type: ApplicationFiled: February 11, 2016Publication date: June 9, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Haruka SAKUMA, Kiwamu SAKUMA, Masahiro KIYOTOSHI
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Patent number: 9293470Abstract: Stack structures are arranged in a first direction horizontal to a semiconductor substrate, one of which has a longitudinal direction along a second direction. One stack structure has a plurality of semiconductor layers stacked between interlayer insulating layers. A memory film is formed on side surfaces of the stack structures and includes a charge accumulation film of the memory cell. Conductive films are formed on side surfaces of the stack structures via the memory film. One stack structure has a shape increasing in width from above to below in a cross-section including the first and third directions. One conductive film has a shape increasing in width from above to below in a cross-section including the second and third directions. Predetermined portions in the semiconductor layers have different impurity concentrations between upper and lower semiconductor layers.Type: GrantFiled: September 19, 2014Date of Patent: March 22, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Haruka Sakuma, Kiwamu Sakuma, Masahiro Kiyotoshi
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Patent number: 9196629Abstract: A memory string includes: a first semiconductor layer formed in a columnar shape extending in a stacking direction perpendicular to a substrate; a tunnel insulating film formed surrounding a side surface of the first semiconductor layer; a charge accumulation film formed surrounding the tunnel insulating film and configured to be capable of accumulating charges; a block insulating film formed surrounding the charge accumulation film; and a plurality of first conductive layers formed surrounding the block insulating film and disposed at a predetermined interval in the stacking direction. The first semiconductor layer comprises carbon-doped silicon and being formed to have different carbon concentrations in upper and lower portions in the stacking direction.Type: GrantFiled: September 19, 2014Date of Patent: November 24, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Haruka Sakuma, Shuichi Toriyama, Masumi Saitoh, Yoshiaki Fukuzumi, Naoki Yasuda
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Publication number: 20150206590Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device and a controller. The system includes the nonvolatile semiconductor memory device including a plurality of memory cells; and the controller configured to control one of read operation, write operation, and a use frequency of the read operation or the write operation on the nonvolatile semiconductor memory device, and configured to change controlling for a memory cell belonging to a first group of the memory cells and to change controlling for a memory cell belonging to a second group located on an upper side or a lower side of the memory cell belonging to the first group.Type: ApplicationFiled: August 20, 2014Publication date: July 23, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Haruka SAKUMA, Yoshiaki Fukuzumi, Hideaki Aochi, Hiroshi Sukegawa, Tokumasa Hara, Hiroshi Yao, Shirou Fujita, Ikuo Magaki, Kiwamu Sakuma, Masumi Saitoh
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Publication number: 20150200200Abstract: Stack structures are arranged in a first direction horizontal to a semiconductor substrate, one of which has a longitudinal direction along a second direction. One stack structure has a plurality of semiconductor layers stacked between interlayer insulating layers. A memory film is formed on side surfaces of the stack structures and include a charge accumulation film of the memory cell. Conductive films are formed on side surfaces of the stack structures via the memory film. One stack structure has a shape increasing in width from above to below in a cross-section including the first and third directions. One conductive film has a shape increasing in width from above to below in a cross-section including the second and third directions. Predetermined portions in the semiconductor layers have different impurity concentrations between upper and lower semiconductor layers.Type: ApplicationFiled: September 19, 2014Publication date: July 16, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Haruka SAKUMA, Kiwamu Sakuma, Masahiro Kiyotoshi
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Publication number: 20150102399Abstract: A memory string includes: a first semiconductor layer formed in a columnar shape extending in a stacking direction perpendicular to a substrate; a tunnel insulating film formed surrounding a side surface of the first semiconductor layer; a charge accumulation film formed surrounding the tunnel insulating film and configured to be capable of accumulating charges; a block insulating film formed surrounding the charge accumulation film; and a plurality of first conductive layers formed surrounding the block insulating film and disposed at a predetermined interval in the stacking direction. The first semiconductor layer comprises carbon-doped silicon and being formed to have different carbon concentrations in upper and lower portions in the stacking direction.Type: ApplicationFiled: September 19, 2014Publication date: April 16, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Haruka Sakuma, Shuichi Toriyama, Masumi Saitoh, Yoshiaki Fukuzumi, Naoki Yasuda
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Publication number: 20150076579Abstract: According to one embodiment, in a semiconductor memory device, a block selection transistor is provided between a stacked body and a word line in a hierarchy selection area. The block selection transistor includes a plurality of semiconductor bodies, a plurality of gate insulating films, and a gate electrode. The plurality of semiconductor bodies respectively extend from the end portions of the respective electrode layers to the respective word lines. The plurality of gate insulating films are provided on the side walls of the respective semiconductor bodies. The gate electrode faces the side wall of the semiconductor body through the gate insulating film.Type: ApplicationFiled: March 2, 2014Publication date: March 19, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masaki TSUJI, Yoshiaki FUKUZUMI, Haruka SAKUMA
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Publication number: 20150035037Abstract: According to one embodiment, the select transistor is provided between a memory array region and the layer selection portion. The channel body and the charge storage film are provided in the memory array region. The select transistor includes a gate electrode provided on a side wall of one of the line portions between the memory array region and the layer selection portion; and a gate insulator film provided between the gate electrode and the line portions. The gate electrode extends in the stacking direction.Type: ApplicationFiled: July 29, 2014Publication date: February 5, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Haruka SAKUMA, Yoshiaki FUKUZUMI