Patents by Inventor Haruki Mori

Haruki Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12025422
    Abstract: An object is to, in a case where it is necessary to share a common coordinate system by a plurality of position measurers, reduce an error in the coordinate system between the position measurers. A position measurement system allows a plurality of laser trackers to share position measurement of a plurality of measurement points. The laser tracker measures three coordinate definition targets for defining a coordinate system of the measurement points, defines a work coordinate system from measurement results of the three coordinate definition targets, and measure the measurement points allocated to the laser tracker using the defined work coordinate system. The other laser trackers and measure the measurement points allocated to the other laser trackers and using correction vectors based on a positional relationship between the laser tracker and the laser trackers and obtained in advance, and the work coordinate system defined by the one laser tracker.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: July 2, 2024
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Junpei Yamaguchi, Masanobu Tsutsui, Haruki Mori
  • Publication number: 20240201951
    Abstract: A method for performing a shift last multiplication and accumulation (MAC) process. A processing circuit can multiply a first input by a first bit of a second input to obtain a first intermediate output. The processing circuit can multiply a third input by a first bit of a fourth input to obtain a second intermediate output. The processing circuit can sum the first and second intermediate outputs to obtain a first sum. The processing circuit can multiply the first input by a second bit of the second input to obtain a third intermediate output. The processing circuit can multiply the third input by a second bit of the fourth input to obtain a fourth intermediate output. The processing circuit can sum the third and fourth intermediate outputs to obtain a second sum. The processing circuit can generate an output by accumulating the first sum and the second sum.
    Type: Application
    Filed: June 9, 2023
    Publication date: June 20, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kinshuk Khare, Hidehiro Fujiwara, Wei-Chang Zhao, Haruki Mori
  • Patent number: 11989046
    Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen, Hung-Jen Liao, Chiting Cheng
  • Publication number: 20240142900
    Abstract: An electrophotographic belt comprising: a substrate and an elastic layer on an outer peripheral surface of the substrate, the elastic layer comprising a cured rubber product including a cured silicone rubber product, an elastic modulus of the elastic layer at a temperature of 23° C. being 1.00 MPa or less, wherein when 1 g sample collected from the elastic layer is immersed in 50 ml of toluene at a temperature of 23° C. for 24 hours in accordance with Japanese Industrial Standard (JIS) K6258:2016, an extract of 3% by mass to 20% by mass with respect to the sample is extracted, and a burning time of the elastic layer in a burn test in accordance with UL94 VTM standard is 30 seconds or less.
    Type: Application
    Filed: October 4, 2023
    Publication date: May 2, 2024
    Inventors: YUSUKE BABA, TAKESHI SUZUKI, MATSUTAKA MAEDA, ATSUSHI HORI, MASAHIRO TAKENAGA, HARUKI MORI, SHOTA INOUE
  • Publication number: 20240104576
    Abstract: According to an embodiment, a method for personal shopping services includes executing a shopping application on a communication terminal to generate transaction data for a sales transaction for a personal shopping service. The transaction data includes commodity information of at least one commodity. The method also includes acquiring prior confirmation request data for the personal shopping service from the transaction data, and then handing over the acquired prior confirmation request data to another application on the communication terminal and causing the other application to transmit the acquired prior request confirmation data to another communication terminal.
    Type: Application
    Filed: July 3, 2023
    Publication date: March 28, 2024
    Inventor: Haruki MORI
  • Publication number: 20240094943
    Abstract: A circuit includes a data register configured to receive and output successive data elements of a plurality of data elements responsive to a clock signal, wherein each data element of the plurality of data elements includes a total number of bits N. A signal generation portion is configured to output a first selection signal responsive to the clock signal, the first selection signal includes two alternating sequences, values of the first sequence increment from zero to N?1, and values of the second sequence decrement from N?1 to zero. A selection circuit coupled to the data register is configured to output the N bits of each data element of the plurality of data elements in a first sequential order responsive to the first sequence of the first selection signal, and in a second sequential order opposite the first sequential order responsive to the second sequence of the first selection signal.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventors: Hidehiro FUJIWARA, Haruki MORI, Wei-Chang ZHAO
  • Patent number: 11935586
    Abstract: A memory device has a memory array of a plurality of memory cells arranged in a plurality of columns and a plurality of rows. The memory cells in each of the plurality of columns include first memory cells and second memory cells alternately arranged along a column direction of the plurality of columns. A first computation circuit is coupled to the first memory cells in each of the plurality of columns, and is configured to generate first output data corresponding to a first computation performed on first weight data stored in the first memory cells. A second computation circuit is coupled to the second memory cells in each of the plurality of columns, and is configured to generate second output data corresponding to a second computation performed on second weight data stored in the second memory cells.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao
  • Patent number: 11908545
    Abstract: A memory device and an operating method for computing-in-memory (CIM) are provided. The memory device for CIM comprises a plurality of memory banks and a global multiply accumulate (MAC) circuit. Each of the memory banks comprises a first memory array, a first latch circuit, a second latch circuit and a local MAC circuit. The first latch circuit latches a first data from the first memory array in a first read cycle. The second latch circuit latches a second data from the first memory array in a second read cycle. The local MAC circuit performs a first stage CIM operation on a first latched data latched in the first latch circuit and the second latched data latched in the second latch circuit to provide a first stage CIM result. The global MAC circuit performs a second stage CIM operation on a plurality of first stage CIM results from the memory banks.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao
  • Publication number: 20240028254
    Abstract: A charge sharing scheme is used to mitigate the variations in cell currents in order to achieve higher accuracy for CIM computing. In some embodiments, a capacitor is associated with each SRAM cell, and the capacitors associated with all SRAM cells in a column are included in averaging the RBL current. In some embodiments, a memory unit associated to an RBL in a CIM device includes a storage element adapted to store a weight, a first switch device connected to the storage element and adapted to be controlled by an input signal and generate a product signal having a magnitude indicative of the product of the input signal and the stored weight. The memory unit further includes a capacitor adapted to receive the product signal and store an amount of charge corresponding to the magnitude of the product signal. The memory unit further include a second switch device adapted to transfer the charge on the capacitor to the RBL.
    Type: Application
    Filed: July 31, 2023
    Publication date: January 25, 2024
    Inventors: Jonathan Tsung-Yung CHANG, Hidehiro FUJIWARA, Hung-Jen LIAO, Yen-Huei CHEN, Yih WANG, Haruki MORI
  • Publication number: 20230418557
    Abstract: A circuit includes a multiplier circuit that receives a signed mantissa of each data element of pluralities of input and weight data elements and generates two's complement products by performing multiplication and reformatting operations on some or all of the input data element signed mantissas and some or all of the weight data element signed mantissas, a summing circuit that receives an exponent of each data element of the pluralities of input and weight data elements and generates sums by adding each input data element exponent to each weight data element exponent, a shifting circuit that shifts each product by an amount equal to a difference between a corresponding sum and a maximum sum, and an adder tree that generates a mantissa sum from the shifted products.
    Type: Application
    Filed: January 20, 2023
    Publication date: December 28, 2023
    Inventors: Chia-Fu LEE, Cheng Han LU, Yu-Der CHIH, Jonathan Tsung-Yung CHANG, Yen-Huei CHEN, Chen-En LEE, Wei-Chang ZHAO, Haruki MORI, Hidehiro FUJIWARA
  • Patent number: 11853596
    Abstract: A circuit includes a data register configured to receive a signal including a plurality of data elements, a first selection circuit coupled to the data register, a counter, a second selection circuit coupled to the counter, and an inverter coupled between the counter and the second selection circuit. The data register outputs a plurality of bits of each data element to the first selection circuit, the counter and the inverter generate complementary signals in which sequential data elements have cyclical values that step in opposite directions, the second selection circuit alternatively outputs each of the complementary signals as a selection signal to the first selection circuit, and the first selection circuit, responsive to the selection signal, outputs the pluralities of bits of the data elements in alternating sequential orders.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao
  • Publication number: 20230410851
    Abstract: Header circuitry for a memory device includes multiple backside power rails that form distinct voltage sources for a plurality of switching devices in the header circuitry. The header circuitry includes at least one region of a first conductivity type. A first section in the first region includes one backside power rail (BPR) that forms a first voltage source that provides a first voltage. A second section in the same first region includes another BPR that forms a second voltage source that provides a second voltage that is different from the first voltage.
    Type: Application
    Filed: July 31, 2023
    Publication date: December 21, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Haruki MORI, Chien-Chi TIEN, Chia-En HUANG, Hidehiro FUJIWARA, Yen-Huei CHEN, Feng-Lun CHEN
  • Publication number: 20230376273
    Abstract: A compute-in-memory device may include a Booth encoder configured to receive at least one input of first bits, a Booth decoder configured to receive at least one weight of second bits and to output a plurality of partial products of the at least one input and the at least one weight, an adder configured to add a first partial product of the plurality of the partial products and a second partial product of the plurality of partial products before the Booth decoder generates a third partial product of the plurality of the partial products and to generate a plurality of sums of partial products, and a carry-lookahead adder configured to add the plurality of sums of partial products and to generate a final sum.
    Type: Application
    Filed: May 20, 2022
    Publication date: November 23, 2023
    Inventors: Rawan Naous, Kerem Akarvardar, Hidehiro Fujiwara, Haruki Mori, Mahmut Sinangil, Yu-Der Chih
  • Patent number: 11815849
    Abstract: It is an object of the present invention to provide an electrophotographic photosensitive member capable of suppressing the environmental fluctuation in the electrical characteristics. The present invention provides the electrophotographic photosensitive member in which the surface layer contains the compound having the specific structure.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: November 14, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Haruki Mori, Naoaki Ichihashi, Kenichi Ikari
  • Publication number: 20230361081
    Abstract: An in-memory computing circuit is provided. The in-memory computing circuit includes a core die, a plurality of conductive pillars, and a plurality of memory dies. The plurality of memory dies are coupled to the core die through the plurality of conductive pillars and are configured to implement computing operation. The plurality of memory dies includes at least one of the memory dies disposed on a bottommost memory die of the plurality of memory dies. The plurality of memory dies receives an input data from the core die through a common input terminal of the core die.
    Type: Application
    Filed: May 4, 2022
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao
  • Publication number: 20230315389
    Abstract: A device includes a first memory cell, a second memory cell, a first logic element, a second logic element, and a third logic element. The first memory cell is configured to store a first bit at a first node, and the second memory cell is configured to store a second bit at a second node. The first logic element includes a first node input terminal coupled to the first node, the second logic element includes a second node input terminal coupled to the second node, and the third logic element includes a first input terminal coupled to a first output terminal of the first logic element and a second input terminal coupled to a second output terminal of the second logic element.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 5, 2023
    Inventors: Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Chia-Fu Lee, Nail Etkin Can AKKAYA, Mahmut Sinangil
  • Publication number: 20230295050
    Abstract: A sintered body includes zirconia, iron, cobalt and titanium, in which a total iron and cobalt content is more than 0.1 mass % and less than 3 mass % and a titanium content is more than 3 mass %.
    Type: Application
    Filed: March 16, 2023
    Publication date: September 21, 2023
    Applicant: TOSOH CORPORATION
    Inventors: Takeshi ITO, Yuji MATSUMURA, Haruki MORI, Hikaru TAKESHIMA, Tomotaka SHIMOYAMA
  • Publication number: 20230267979
    Abstract: A memory device and an operating method for computing-in-memory (CIM) are provided. The memory device for CIM comprises a plurality of memory banks and a global multiply accumulate (MAC) circuit. Each of the memory banks comprises a first memory array, a first latch circuit, a second latch circuit and a local MAC circuit. The first latch circuit latches a first data from the first memory array in a first read cycle. The second latch circuit latches a second data from the first memory array in a second read cycle. The local MAC circuit performs a first stage CIM operation on a first latched data latched in the first latch circuit and the second latched data latched in the second latch circuit to provide a first stage CIM result. The global MAC circuit performs a second stage CIM operation on a plurality of first stage CIM results from the memory banks.
    Type: Application
    Filed: February 24, 2022
    Publication date: August 24, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao
  • Publication number: 20230260569
    Abstract: A memory device has a memory array of a plurality of memory cells arranged in a plurality of columns and a plurality of rows. The memory cells in each of the plurality of columns include first memory cells and second memory cells alternately arranged along a column direction of the plurality of columns. A first computation circuit is coupled to the first memory cells in each of the plurality of columns, and is configured to generate first output data corresponding to a first computation performed on first weight data stored in the first memory cells. A second computation circuit is coupled to the second memory cells in each of the plurality of columns, and is configured to generate second output data corresponding to a second computation performed on second weight data stored in the second memory cells.
    Type: Application
    Filed: February 11, 2022
    Publication date: August 17, 2023
    Inventors: Hidehiro FUJIWARA, Haruki MORI, Wei-Chang ZHAO
  • Publication number: 20230259330
    Abstract: A device including: a first adder having first adder inputs and first adder outputs; a first register having first register inputs and first register outputs, the first register inputs coupled to the first adder outputs; a second register having second register inputs and second register outputs, the second register inputs coupled to the first adder outputs; and a second adder having second adder inputs and second adder outputs and configured to receive register output signals from the first register outputs and the second register outputs. Wherein, the first adder is configured to calculate a first sum of a first input value and a second input value, and the first register is configured to store the first sum, and the first adder is configured to calculate a second sum of a third input value and a fourth input value, and the second register is configured to store the second sum.
    Type: Application
    Filed: May 13, 2022
    Publication date: August 17, 2023
    Inventors: Haruki Mori, Wei-Chang Zhao, Hidehiro Fujiwara