Patents by Inventor Harunobu KISHIDA

Harunobu KISHIDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11074370
    Abstract: A host device includes a power supply unit configured to supply power to a SoC, a current measurement circuit configured to measure a current from the power supply unit to the SoC, a detection unit configured to detect a power supply glitch in the host device, on the basis of a result of current measurement by the current measurement circuit, and a controller configured to suspend transmission of encrypted command from the host device to the memory device if the detection unit detects a power supply glitch in the host device.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: July 27, 2021
    Assignee: MEGACHIPS CORPORATION
    Inventors: Takahiko Sugahara, Naoki Matsuyama, Harunobu Kishida
  • Patent number: 11009535
    Abstract: A circuitry is configured to calculate a measured average value based on measured current values obtained in a target period for determination, and determine whether a memory device is an authorized or an unauthorized product, based on a comparison result between a measured average value and a reference average value.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: May 18, 2021
    Assignee: MEGACHIPS CORPORATION
    Inventors: Takahiko Sugahara, Harunobu Kishida
  • Patent number: 10509565
    Abstract: Upon receiving an erase command and a first logical address, a controller in a first mode sets, as an erasure waiting area, an erasure unit area assigned with a first physical address associated with the first logical address in a first table. The controller in the first mode replaces, in the first table, the first physical address with a physical address assigned to an erasure completion area. The controller in a second mode sets the erasure waiting area as the erasure completion area. Upon receiving a release command to release the second mode at some point in time of data erasure from the erasure waiting area, the controller changes the operation mode to a third mode. The controller operating in the third mode erases un-erased data from the erasure waiting area and changes the operation mode from the third mode to the first mode.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: December 17, 2019
    Assignee: MEGACHIPS CORPORATION
    Inventors: Harunobu Kishida, Masayuki Imagawa
  • Publication number: 20190278945
    Abstract: A host device includes a power supply unit configured to supply power to a SoC, a current measurement circuit configured to measure a current from the power supply unit to the SoC, a detection unit configured to detect a power supply glitch in the host device, on the basis of a result of current measurement by the current measurement circuit, and a controller configured to suspend transmission of encrypted command from the host device to the memory device if the detection unit detects a power supply glitch in the host device.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 12, 2019
    Applicant: MegaChips Corporation
    Inventors: Takahiko SUGAHARA, Naoki MATSUYAMA, Harunobu KISHIDA
  • Publication number: 20190195925
    Abstract: A circuitry is configured to calculate a measured average value based on measured current values obtained in a target period for determination, and determine whether a memory device is an authorized or an unauthorized product, based on a comparison result between a measured average value and a reference average value.
    Type: Application
    Filed: December 24, 2018
    Publication date: June 27, 2019
    Applicant: MegaChips Corporation
    Inventors: Takahiko SUGAHARA, Harunobu KISHIDA
  • Publication number: 20180165012
    Abstract: Upon receiving an erase command and a first logical address, a controller in a first mode sets, as an erasure waiting area, an erasure unit area assigned with a first physical address associated with the first logical address in a first table. The controller in the first mode replaces, in the first table, the first physical address with a physical address assigned to an erasure completion area. The controller in a second mode sets the erasure waiting area as the erasure completion area. Upon receiving a release command to release the second mode at some point in time of data erasure from the erasure waiting area, the controller changes the operation mode to a third mode. The controller operating in the third mode erases un-erased data from the erasure waiting area and changes the operation mode from the third mode to the first mode.
    Type: Application
    Filed: December 7, 2017
    Publication date: June 14, 2018
    Applicant: MegaChips Corporation
    Inventors: Harunobu KISHIDA, Masayuki IMAGAWA