Abstract: A semiconductor memory device comprises first and second memory sections including a plurality of memory elements, and a memory control section for allowing a data transfer operation between the first and second memory sections based on an external control command while allowing a memory operation to at least one of the first and second memory sections. At least one of the first and second memory sections include a plurality of small memory regions, and the memory control section allows each of the plurality of small memory regions to be separately and simultaneously subjected to an access operation.

Abstract: A non-volatile semiconductor memory device, comprises a plurality of memory banks each including a plurality of memory cells, a command recognition section for identifying an externally input command signal and outputting an identification signal, an internal control section for generating a control signal for executing a command designated by the identification signal, an address control section for generating an internal address signal to a memory region including an arbitrary combination of the plurality of memory banks to be accessed, based on the externally input address signal, and a first address inversion section for inverting or non-inverting the logical values of at least a specific bit of the input address signal and outputting the resultant input address signal to the address control section. Predetermined memory cells are accessed based on the control signal and the internal address signal.

Abstract: A data transfer control device of the present invention includes: a command recognition section for recognizing the input control command; a first address output section for controlling an output and storage order of the data transfer addresses and the data transfer completion address based on the input control command; a first memory address storage section for storing the data transfer start address of the first memory array output from the first address output section; a second memory address storage section for storing the data transfer start address of the second memory array output from the first address output section; a third memory address storage section for storing the data transfer completion address output from the first address output section.

Abstract: A semiconductor memory device in which an input command controls an operation includes a command state machine for decoding the input command and outputting the decoding result; a plurality of status registers for storing state information of the semiconductor memory device; a first switching circuit for receiving data from the plurality of status registers, and selectively outputting the data from at least one of the plurality of status registers to a first data bus; and a second switching circuit for receiving the data on the first data bus and data from a sense amplifier, and selectively outputting either one of data to a second data bus. At least the first switching circuit, among the first and second switching circuits, is controlled by the decoding result output by the command state machine.

Abstract: A semiconductor storage device includes: a plurality of first memory arrays each including a plurality of semiconductor storage elements, in which data from an external device is written, and from which the data is read out to the external device, a second memory array which operates separately from the plurality of first memory arrays and which includes at least one block including a plurality of non-volatile semiconductor storage elements; and a data transfer section for transferring the data between the plurality of first memory arrays and the second memory array.

Abstract: A semiconductor memory device in which an input command controls an operation includes a command state machine for decoding the input command and outputting the decoding result; a plurality of status registers for storing state information of the semiconductor memory device; a first switching circuit for receiving data from the plurality of status registers, and selectively outputting the data from at least one of the plurality of status registers to a first data bus; and a second switching circuit for receiving the data on the first data bus and data from a sense amplifier, and selectively outputting either one of data to a second data bus. At least the first switching circuit, among the first and second switching circuits, is controlled by the decoding result output by the command state machine.

Abstract: A non-volatile semiconductor memory device, comprises a plurality of memory banks each including a plurality of memory cells, a command recognition section for identifying an externally input command signal and outputting an identification signal, an internal control section for generating a control signal for executing a command designated by the identification signal, an address control section for generating an internal address signal to a memory region including an arbitrary combination of the plurality of memory banks to be accessed, based on the externally input address signal, and a first address inversion section for inverting or non-inverting the logical values of at least a specific bit of the input address signal and outputting the resultant input address signal to the address control section. Predetermined memory cells are accessed based on the control signal and the internal address signal.

Abstract: A data transfer control device of the present invention includes: a command recognition section for recognizing the input control command; a first address output section for controlling an output and storage order of the data transfer addresses and the data transfer completion address based on the input control command; a first memory address storage section for storing the data transfer start address of the first memory array output from the first address output section; a second memory address storage section for storing the data transfer start address of the second memory array output from the first address output section; a third memory address storage section for storing the data transfer completion address output from the first address output section.

Abstract: A semiconductor memory device comprises first and second memory sections including a plurality of memory elements, and a memory control section for allowing a data transfer operation between the first and second memory sections based on an external control command while allowing a memory operation to at least one of the first and second memory sections. At least one of the first and second memory sections include a plurality of small memory regions, and the memory control section allows each of the plurality of small memory regions to be separately and simultaneously subjected to an access operation.

Abstract: A semiconductor storage device includes: a plurality of first memory arrays each including a plurality of semiconductor storage elements, in which data from an external device is written, and from which the data is read out to the external device, a second memory array which operates separately from the plurality of first memory arrays and which includes at least one block including a plurality of non-volatile semiconductor storage elements; and a data transfer section for transferring the data between the plurality of first memory arrays and the second memory array.

Abstract: A non-volatile memory device includes: a plurality of memory cell arrays including a plurality of blocks, each block including a matrix of memory cells coupled to one another via word lines and bit lines such that corresponding ones of the word line in the plurality of blocks of each memory cell array are coupled to a common, the word lines being commonly driven by decoders respectively provided for the memory cell arrays, where all data stored in each block is subject to erasure in one erase operation, the non-volatile memory device further including: a plurality of sense amplifiers for reading data from the memory cells; and a control circuit for simultaneously performing a plurality of operations by using the plurality of sense amplifiers.

Abstract: In a charge pump for providing a desired boosted output voltage, a plurality of boosting stages are connected in series. The pump also has a clock signal supply circuit for providing clock signals and a boost circuit for boosting the clock signals. Clock signals derived from the clock signal supply circuit are supplied to each of the boosting stages on a former side. In contrast, a boosted clock signal derived from the clock signal boost circuit and a clock signal derived from the clock signal supply circuit are supplied to each of the boosting stages on a latter side.