Abstract: In an integrated circuit comprising an IIL and a high frequency npn bipolar transistor which has a deep p.sup.- -type base region 45 for its inverted npn output transistors, circuit elements such as a resistor part R, a capacitor part C, a diode part D and an isolated crossing connection part Cr are provided with deep p.sup.- -type regions 54, 54', 65', 71 and 82 which are formed at the same time with the p.sup.- -type region 45 in the IIL, and thereby, reliability of the circuit elements as well as characteristic thereof are improved, thereby further improving manufacturing yields.

Abstract: Analog-to-digital conversion method and device using triangular vertex solution are disclosed. The method includes the steps of defining a first and a second boundary value between which a quantity to be analog-to-digital converted resides, multiplying a difference between the first boundary value and the quantity to be converted by a first coefficient to produce a first physical quantity, multiplying a difference between the second boundary value and the quantity to be converted by a second coefficient to produce a second physical quantity, comparing the first and second physical quantities to obtain a comparison result, and logically converting the comparison result into a digital value.

Abstract: A parallel type analog to digital (A/D) converter in which an input signal and reference voltages are differentially amplified by differential converting circuits, interpolation resistors are inserted between the outputs and between the complementary outputs of the differential converting circuits, and a tap voltage between the interpolation resistors is A/D converted, so that the A/D converter can operate at a high accuracy and at a high speed.

Abstract: A dynamic logic gate includes a precharge device for precharging the logic gate in synchronism with a clock; a partial logic gate arranged such that, depending on the logic states of the logic inputs, current is allowed to flow between its two terminals or is cut off; a bipolar transistor whose emitter is grounded, and a discharge device for discharging the charge stored in the base of the bipolar transistor during the precharge period. The logic gate speeds up the logic operation by suddenly discharging the load capacity of the circuitry by supplying the conducting current of the partial logic gate to the bipolar transistor base and using the high speed current amplification action of the bipolar transistor.

Abstract: A dynamic logic gate includes a precharge device for precharging the logic gate in synchronism with a clock; a partial logic gate arranged such that, depending on the logic states of the logic inputs, current in allowed to flow between its two terminals or is cut off; a bipolar transistor whose emitter is grounded, and a discharge device for discharging the charge stored in the base of the bipolar transistor during the precharge period. The logic gate speeds up the logic operation by suddenly discharging the load capacity of the circuitry by supplying the conducting current of the partial logic gate to the bipolar transistor base and using the high speed current amplification action of the bipolar transistor.

Abstract: In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p.sup.- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p.sup.- -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in FIG. 9, p.sup.- -regions (40) and (49) are formed simultaneously with the p.sup.- -collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting IIL of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p.sup.- -region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h.sub.

Abstract: The invention relates to a BIMOS logic gate comprising: a bipolar transistor; and depletion type MOS transistors whose sources are connected to a base of the bipolar transistor or MOS transistors having a threshold voltage smaller than that of MOS transistors constructing another complementary type logic circuit. A current of the bipolar transistor flows at an input voltage lower than that of the related art BIMOS logic gate and the current can be cut off by an input voltage which is equal to that of the ordinary complementary type logic circuit. Thus, the gate operates at a low electric power and can operate at a high speed at a low power source voltage.

Abstract: A serial-parallel type a/d converter comprises first comparators whose one input is supplied with an input signal, for producing upper-digit signals; a circuit for supplying first different potentials determined according to arithmetic progression with respect to a reference potential to respective another input of the first comparators when the control signal is of first state, and for producing N-1 second different potentials with difference 1/N of voltage difference of first potentials over potential P (N, P: natural numbers) given by the upper-digit signals when the control signal is of second state; and N-1 second comparators whose one input is supplied with the input signal and another input is supplied with the respective second different potentials for producing lower-digit signals.

Abstract: A parallel type A/D converter includes circuitry for generating plural reference voltages, comparators for comparing the plural reference voltages with an input voltage, logic circuits for logically processing the outputs of comparators, and an encoder circuit for encoding the outputs from the logic circuits. A pair of logic outputs are obtained by a first logic circuit chain for receiving as inputs the outputs of a comparator of number i and of a comparator i+2. Conversion errors are reduced by properly processing this pair of logic outputs in a second logic circuit, or by composing an encoder circuit for receiving the pair of logic outputs as inputs.

Abstract: An image signal processor which includes a local image register for receiving local image area data of m rows.times.n columns pixels, and a expansion use register of m row.times.1 column pixels coupled to the output of the local image register. Thereby, expansion of local image area, and parallel processing can be readily conducted.

Abstract: In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p.sup.- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p.sup.- -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in FIG. 9, p.sup.- -regions (40) and (49) are formed simultaneously with the p.sup.- -collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting IIL of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p.sup.- -region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h.sub.

Abstract: An image signal processor which includes a local image register for receiving local image area data of m rows.times.n columns pixels, and a expansion use register of m row.times.l column pixels coupled to the output of the local image register. Thereby, expansion of local image area, and parallel processing can be readily conducted.

Abstract: To extend the function of a bipolar type RAM, a register function is added to the RAM function. The register function is such that the contents stored in a memory cell is inputted to a differential switch, and the output to the differential switch is derived out to constantly read out the stored content of a desired bit with a simple circuit construction.

Abstract: This invention provides parallel partial image processing such as spatial convolution or non-linear neighbor arithmetic operation using an image processor which can easily be formed as a large-scale integrated circuit and can be used for various purposes. The image processor has an adder-subtractor, a multiplier, a reciprocal number memory in which the reciprocal of an address and the amount of shift are stored at each address, and a shift register. The processor therefore is capable of high-speed dividing operations by multiplying a multiplicant by the reciprocal of a multiplier and by shifting the result of the multiplication. Also, by switching the inputs to the adder-subtractor and to the multiplier rapidly under program control, it is possible to perform arbitrary addition, subtraction, multiplication and division on partial image data of m rows and n columns stored in a partial image memory of the image processor.

Abstract: A semiconductor integrated circuit device in which the side surfaces of an emitter of an oxide isolated bipolar transistor are surrounded with insulating compounds or regions so that the capacitance between the emitter and base is lowered and a base is formed by the self-alignment so that the influence of an active base between an external base and the emitter can be made negligible. Thus the base resistance and parasitic capacitance are lowered.

Abstract: In a stacked, multilayer IIL (integrated injection logic) circuit, with which power consumption can be significantly reduced, a discharging circuit constructed of an IIL constant-current circuit or of a resistor is provided for one of transistors which are used for shifting the level of a signal from an IIL circuit of a top layer to an IIL circuit of a bottom layer, so that signal transmission therebetween is prevented from deterioration. A charging circuit may be added to another transistor, while a diode may be interposed between these transistors. Additional diodes may be interposed between adjacent layers for speeding up the signal transmission from one layer to another upper layer.

Abstract: A first logic circuit comprises coupling gate circuits driven by clock pulses of different phases, flip-flop circuits cascade-connected via the coupling gate circuits and feedback circuits for feeding back the outputs of the flip-flop circuits to the preceding stage flip-flop circuits, and generates pulse sequences of different phases. A second logic circuit further comprises latch circuits one for each of the flip-flop circuits, driven by the pulse sequences generated by the first logic circuit. Those logic circuits are useful to a successive approximation register of a successive approximation A/D converter.

Abstract: A parallel type A/D converter capable of operating at an extremely high speed with a high degree of accuracy and with low power consumption. A plurality of comparators each having a reference voltage corresponding to an assigned quantizing level are disposed in parallel with each other and divided into a plurality of comparator blocks or groups. A plurality of sub-comparators are provided so that prior to the comparison of the input signal by the comparators, the input signal is first compared with the reference voltages of the sub-comparators and in response to the output from the sub-comparator having the reference voltage comparable or corresponding to the incoming input signal, only the comparators in the comparator block or group associated with said sub-comparator are energized or enabled while the remaining comparators are kept de-energized or disabled, whereby a minimum power consumption may be attained.

Abstract: An IC device comprising a junction type field effect transistor of a back gate type and a bipolar device such as a bipolar transistor and a resistor made of impurity diffused region, wherein an extremely thin (in the order of 0.05-0.2 .mu.m) impurity doped surface region of a conductivity type same as that of a back gate region is formed at the surface of a surface channel region, and is separated from at least a drain region to sustain high breakdown voltage between gate region and the drain region; the impurity surface region serving to reduce noise and also enabling to achieve satisfactory characteristics of J-FET and also good ohmic characteristics of the resistor.

Abstract: A ghost signal cancellation system for cancelling ghost signals caused, for example, by reflection in a transmission line of television signals transmitted from a television transmitting station. This system is particularly suited for incorporation in a television receiver to improve the picture quality of a reproduced picture.