Abstract: An analog to digital converter comprising: a plurality of voltage generators, each voltage generator having a control input and being capable of generating an output whose voltage is dependent on a signal applied to the control input; a comparison stage arranged to compare the input signal with one or more outputs of the voltage generators and generate one or more comparator outputs indicative of the result(s) of the comparison(s); and a controller arranged to receive the comparator outputs, the controller being configured to: (i) signal the control inputs of a number V1 of the voltage generators, and estimate a number B1 of bits of the digital representation; and subsequently (ii) signal the control input(s) of a number V2 of the voltage generators, and estimate a number B2 of bits of the digital representation; wherein V2 is less than V1.

Abstract: An analog to digital converter comprising: a plurality of voltage generators, each voltage generator having a control input and being capable of generating an output whose voltage is dependent on a signal applied to the control input; a comparison stage arranged to compare the input signal with one or more outputs of the voltage generators and generate one or more comparator outputs indicative of the result(s) of the comparison(s); and a controller arranged to receive the comparator outputs, the controller being configured to: (i) signal the control inputs of a number V1 of the voltage generators, and estimate a number B1 of bits of the digital representation; and subsequently (ii) signal the control input(s) of a number V2 of the voltage generators, and estimate a number B2 of bits of the digital representation; wherein V2 is less than V1.

Abstract: A variable frequency oscillator includes an inductance unit having a first inductance, a first variable capacitor coupled across the inductance unit, and a second variable capacitor coupled across a part of the inductance unit. The inductance of the part of the inductance unit coupled by the second variable capacitor is a proportion of the first inductance.

Abstract: Methods of measuring capacitance error in a successive approximation register (SAR) analog to digital converter (ADC) are described, including a method in which said ADC includes a register and a digital to analog converter (DAC), and the method comprises connecting a first capacitance associated with a first bit of the DAC between a first reference voltage and a second reference voltage, connecting a first set of one or more capacitances associated with one or more other bits of the DAC between the first reference voltage and a third reference voltage, connecting the first capacitance between a first node and the third reference voltage, connecting the first set of one or more capacitances between the first node and the second reference voltage, and measuring a voltage at the first node to determine a representation of a difference between the first capacitance and a total capacitance of the first set of one or more capacitances.

Abstract: Methods of measuring capacitance error in a successive approximation register (SAR) analog to digital converter (ADC) are described, including a method in which said ADC includes a register and a digital to analog converter (DAC), and the method comprises connecting a first capacitance associated with a first bit of the DAC between a first reference voltage and a second reference voltage, connecting a first set of one or more capacitances associated with one or more other bits of the DAC between the first reference voltage and a third reference voltage, connecting the first capacitance between a first node and the third reference voltage, connecting the first set of one or more capacitances between the first node and the second reference voltage, and measuring a voltage at the first node to determine a representation of a difference between the first capacitance and a total capacitance of the first set of one or more capacitances.

Abstract: A variable gain amplifier circuit (200) comprising an amplifier element (202) having an input (208, 210) and an output (220, 222); a feedback loop (224, 226) having a feedback impedance (228, 230) connected between the input (208, 210) and output (232, 234) of the amplifier element (202); an input branch (212, 214) having an input resistance connected between an input of the variable gain amplifier circuit and the input (208, 210) of the amplifier element (202); and a plurality of switches for selecting a gain of the variable gain amplifier circuit (200); characterised in that the variable gain amplifier circuit (200) further comprises an intermediate element (204) having an input and an output, the input being connected to a node between one of the switches and the feedback impedance (228, 230), such that the output can provide a signal which can be used to attenuate a signal component in the output (220, 222) of the amplifier element (202) caused by a non-linearity in the plurality of switches.

Abstract: An analog-to-digital converter employs one or more reference ladders for generating reference voltages with which to compare the analog signal for quantization. Selected impedances of the reference ladder can be dynamically decoupled from the input signal in dependence on the value of the output signal in order to reduce headroom in the reference ladders, thus making possible accurate quantization in low-voltage applications.

Abstract: An analogue-to-digital converter employs one or more reference ladders for generating reference voltages with which to compare the analogue signal for quantization. Selected impedances of the reference ladder can be dynamically decoupled from the input signal in dependence on the value of the output signal in order to reduce headroom in the reference ladders, thus making possible accurate quantization in low-voltage applications.

Abstract: A circuit for modulating an input signal including a dither signal generator configured to generate a first dither signal having a maximum amplitude, a deamplifier configured to reduce the amplitude of said input signal so as to generate a deamplified input signal having a maximum amplitude that is comparable to the maximum amplitude of the dither signal, and a summer configured to sum the dither signal with the deamplified input signal.

Abstract: A circuit for modulating an input signal including a dither signal generator configured to generate a first dither signal having a maximum amplitude, a deamplifier configured to reduce the amplitude of said input signal so as to generate a deamplified input signal having a maximum amplitude that is comparable to the maximum amplitude of the dither signal, and a summer configured to sum the dither signal with the deamplified input signal.

Abstract: The present invention relates to a multi-bit digital to analogue converter (DAC) and to a delta-sigma analogue to digital converter employing such a DAC. The DAC has a multi-bit input, a plurality of elements for processing an input signal received at the input and a selector for selecting, based on the input signal, one or more of the DAC elements to process the signal. The DAC has control means for controlling the selector such that if the input to the DAC is below a predetermined level for a predetermined period of time the selector is operative to select only a single one of the DAC elements to process the input signal. Also disclosed is a delta-sigma analogue to digital converter (ADC) employing such a DAC.

Abstract: A variable frequency oscillator includes an inductance unit having a first inductance, a first variable capacitor coupled across the inductance unit, and a second variable capacitor coupled across a part of the inductance unit. The inductance of the part of the inductance unit coupled by the second variable capacitor is a proportion of the first inductance.

Abstract: A delta sigma analogue to digital converter comprising: an integrator having first and second differential inputs for receiving an input analogue signal, the integrator having differential outputs; a quantiser having first and second differential inputs which receive signals output by the integrator, and an output which provides a digital output signal of the delta sigma analogue to digital converter, and a digital to analogue converter. The digital to analogue converter has an input which is connected to an output of the delta sigma analogue to digital converter, and first and second differential outputs. The first output of the digital to analogue converter is connected to the first input of the integrator such that if the second output of the digital to analogue converter is not connected to the second input of the integrator and the second input of the integrator is connected to a fixed reference voltage the delta sigma analogue to digital converter is able to operate in a single-ended mode.

Abstract: A variable gain amplifier includes an integrator having an input, an output and a feedback loop connected between the input and output, a plurality of input chains connected in parallel between the amplifier input and the input of the integrator, each input chain including a resistor and a first switch and a plurality of second switches, each second switch connected between an intermediate node between the resistor and first switch of a respective input chain and the feedback loop of the integrator, wherein the resistance of the resistors in the input chains is scaled by a scaling factor with respect to one another and the on-resistances of the first and second switches connected to each intermediate node are scaled by the corresponding scaling factor.

Abstract: A variable gain amplifier circuit (200) comprising an amplifier element (202) having an input (208, 210) and an output (220, 222); a feedback loop (224, 226) having a feedback impedance (228, 230) connected between the input (208, 210) and output (232, 234) of the amplifier element (202); an input branch (212, 214) having an input resistance connected between an input of the variable gain amplifier circuit and the input (208, 210) of the amplifier element (202); and a plurality of switches for selecting a gain of the variable gain amplifier circuit (200); characterised in that the variable gain amplifier circuit (200) further comprises an intermediate element (204) having an input and an output, the input being connected to a node between one of the switches and the feedback impedance (228, 230), such that the output can provide a signal which can be used to attenuate a signal component in the output (220, 222) of the amplifier element (202) caused by a non-linearity in the plurality of switches.

Abstract: An integrator based on an amplifier having a capacitive element connected between the input and the output of the amplifier, with a resistive element connected in series with the capacitive element. Integrators of this type can be used in feed-forward structures of delta-sigma analogue-to-digital converters in order to avoid the need for adders to combine the outputs of parallel signal paths in the feed-forward structure.

Abstract: The present invention relates to a multi-bit digital to analogue converter (DAC) and to a delta-sigma analogue to digital converter employing such a DAC. The DAC has a multi-bit input, a plurality of elements for processing an input signal received at the input and a selector for selecting, based on the input signal, one or more of the DAC elements to process the signal. The DAC has control means for controlling the selector such that if the input to the DAC is below a predetermined level for a predetermined period of time the selector is operative to select only a single one of the DAC elements to process the input signal. Also disclosed is a delta-sigma analogue to digital converter (ADC) employing such a DAC.

Abstract: A variable gain amplifier includes an integrator having an input, an output and a feedback loop connected between the input and output, a plurality of input chains connected in parallel between the amplifier input and the input of the integrator, each input chain including a resistor and a first switch and a plurality of second switches, each second switch connected between an intermediate node between the resistor and first switch of a respective input chain and the feedback loop of the integrator, wherein the resistance of the resistors in the input chains is scaled by a scaling factor with respect to one another and the on-resistances of the first and second switches connected to each intermediate node are scaled by the corresponding scaling factor.

Abstract: A delta sigma analogue to digital converter comprising: an integrator having first and second differential inputs for receiving an input analogue signal, the integrator having differential outputs; a quantiser having first and second differential inputs which receive signals output by the integrator, and an output which provides a digital output signal of the delta sigma analogue to digital converter, and a digital to analogue converter. The digital to analogue converter has an input which is connected to an output of the delta sigma analogue to digital converter, and first and second differential outputs. The first output of the digital to analogue converter is connected to the first input of the integrator such that if the second output of the digital to analogue converter is not connected to the second input of the integrator and the second input of the integrator is connected to a fixed reference voltage the delta sigma analogue to digital converter is able to operate in a single-ended mode.

Abstract: A method of Digital to Analogue conversion of an input signal Do for suppressing the effect of clock-jitter in a Delta-Sigma analogue to digital converter, or class D amplifier, comprises charging a capacitor to a reference voltage value (Vref) during a first phase (?) of a clock signal, discharging the capacitor during a second phase (?2) of the clock signal, wherein the discharge is regulated by a biased transistor, responsive to the voltage on the capacitor, in a first part of the second phase to provide an approximately constant discharge current, and regulated in a second part of the second phase for rapidly discharging the capacitor before the end of the second phase; and providing an output (Ud, OUT) as a function of the discharge current and the input signal Do. The output signal Ud, may be applied as a feedback signal to a loop filter in a Delta-Sigma converter. Alternatively, the output may represent the output of a Class D amplifier.