Patents by Inventor Hau-Tai Shieh
Hau-Tai Shieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9865335Abstract: A memory device comprises a tracking control circuit for controlling the write operation or the read operation of the memory device. The tracking control circuit comprises a plurality of tracking cells, wherein the timing characteristics of the tracking cells emulate the timing characteristics of a bit cell during a write operation or a read operation of the memory device. The memory device further comprises at least two reference word lines for configuring the number of tracking cells of the tracking control circuit; and a selection circuit configured to activate one or more of the at least two reference word lines.Type: GrantFiled: February 3, 2017Date of Patent: January 9, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTDInventors: Pankaj Aggarwal, Jui-Che Tsai, Cheng Hung Lee, Chien-Yuan Chen, Chiting Cheng, Hau-Tai Shieh, Yi-Tzu Chen
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Patent number: 9858987Abstract: A sense amplifier circuit includes a pair of data lines, a pair of inverters, and a data line charging circuit. Each of the inverters is connected to a respective one of the data lines. The data line charging circuit includes a transistor. The transistor has a source/drain terminal connected to one of the data lines and a gate terminal connected to the other of the data lines.Type: GrantFiled: May 14, 2015Date of Patent: January 2, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimiedInventors: Chien-Yuan Chen, Hau-Tai Shieh
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Publication number: 20170272075Abstract: A circuit is disclosed. The circuit includes eight MOD transistors and a capacitor, the first MOS transistor having a source coupled to a first predetermined supply voltage (VDDM), a second MOS transistor having a source coupled to a first predetermined supply voltage VDDM, a third MOS transistor having a source coupled to a drain of the first MOS transistor, a fourth MOS transistor having a source coupled to a drain of the second MOS transistor, a fifth MOS transistor having a source coupled to a drain of the third MOS transistor and a gate of the second MOS transistor, and a gate coupled to a gate of the third MOS transistor and an input node, and a drain coupled to ground, a sixth MOS transistor having a source coupled to a drain of the fourth MOS transistor and a gate of the first MOS transistor and an output node.Type: ApplicationFiled: March 18, 2016Publication date: September 21, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao, Hau-Tai Shieh, Che-Ju Yeh
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Publication number: 20170148508Abstract: A memory device comprises a tracking control circuit for controlling the write operation or the read operation of the memory device. The tracking control circuit comprises a plurality of tracking cells, wherein the timing characteristics of the tracking cells emulate the timing characteristics of a bit cell during a write operation or a read operation of the memory device. The memory device further comprises at least two reference word lines for configuring the number of tracking cells of the tracking control circuit; and a selection circuit configured to activate one or more of the at least two reference word lines.Type: ApplicationFiled: February 3, 2017Publication date: May 25, 2017Inventors: PANKAJ AGGARWAL, JUI-CHE TSAI, CHENG HUNG LEE, CHIEN-YUAN CHEN, CHITING CHENG, HAU-TAI SHIEH, YI-TZU CHEN
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Patent number: 9654146Abstract: A parity bit generator module is disclosed that operates in a first direction or a second direction. In the first direction, the parity bit generator module generates parity bits for a first input datastream having information bits and combines these parity bits with the information bits of the input datastream to provide a first output datastream. Otherwise in a second direction, the parity bit generator module separates information bits from a second input datastream and generates parity bits from the information bits of the second input datastream to provide a second output datastream having the parity bits. In various exemplary embodiments, the bi-directional parity bit generator is implemented as part of an encoding/decoding module and/or an error-correcting code (ECC) data storage device.Type: GrantFiled: August 18, 2015Date of Patent: May 16, 2017Assignee: Taiwan Semiconductor Manufacturing Company, LTD.Inventors: Yi-Tzu Chen, Chien-Yuan Chen, Hau-Tai Shieh
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Publication number: 20170133387Abstract: Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell.Type: ApplicationFiled: January 20, 2017Publication date: May 11, 2017Inventors: Chien-Yu Huang, Chien-Yuan Chen, Hau-Tai Shieh
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Patent number: 9583181Abstract: A memory device comprises a tracking control circuit for controlling the write operation or the read operation of the memory device. The tracking control circuit comprises a plurality of tracking cells, wherein the timing characteristics of the tracking cells emulate the timing characteristics of a bit cell during a write operation or a read operation of the memory device. The memory device further comprises at least two reference word lines for configuring the number of tracking cells of the tracking control circuit; and a selection circuit configured to activate one or more of the at least two reference word lines.Type: GrantFiled: October 1, 2015Date of Patent: February 28, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Pankaj Aggarwal, Jui-Che Tsai, Cheng Hung Lee, Chien-Yuan Chen, Chiting Cheng, Hau-Tai Shieh, Yi-Tzu Chen
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Publication number: 20170054454Abstract: A parity bit generator module is disclosed that operates in a first direction or a second direction. In the first direction, the parity bit generator module generates parity bits for a first input datastream having information bits and combines these parity bits with the information bits of the input datastream to provide a first output datastream. Otherwise in a second direction, the parity bit generator module separates information bits from a second input datastream and generates parity bits from the information bits of the second input datastream to provide a second output datastream having the parity bits. In various exemplary embodiments, the bi-directional parity bit generator is implemented as part of an encoding/decoding module and/or an error-correcting code (ECC) data storage device.Type: ApplicationFiled: August 18, 2015Publication date: February 23, 2017Applicant: Taiwan Semiconductor Manufacturing Company, LTD.Inventors: Yi-Tzu CHEN, Chien-Yuan CHEN, Hau-Tai SHIEH
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Patent number: 9558791Abstract: Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell.Type: GrantFiled: December 5, 2013Date of Patent: January 31, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chien-Yu Huang, Chien-Yuan Chen, Hau-Tai Shieh
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Patent number: 9501079Abstract: An apparatus comprises a first signal input, a first transistor, a first line, a first circuit coupled to the first transistor through the first line, a second line coupled to the first line between the first transistor and the first circuit, a second transistor coupled to the first transistor through the second line, a second circuit coupled to the second transistor, the first circuit being a replica of the second circuit, a second signal input, and a third transistor coupled to the second signal input and the second circuit. The apparatus maintains a virtual voltage of the second circuit above a predetermined threshold by a voltage associated with the second line. The voltage associated with the second line is based on a difference between a first current associated with a portion of the first line and a second current associated with another portion of the first line.Type: GrantFiled: November 1, 2013Date of Patent: November 22, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Yuan Chen, Hau-Tai Shieh
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Patent number: 9330731Abstract: A circuit comprises a first transistor and a second transistor in a strap cell region between a first memory array and a second memory array of a memory device. The first transistor includes a first node connected to a first data line, and a second node connected to a second data line. The first node and the second node of the first transistor are complementary to each other in voltage level. Further, the second transistor includes a first node connected to the second data line, and a second node connected to the first data line. The first node and the second node of the second transistor are complementary to each other in voltage level.Type: GrantFiled: February 17, 2014Date of Patent: May 3, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hua-Hsin Yu, Hsiu Fen Peng, Hau-Tai Shieh
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Patent number: 9299420Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.Type: GrantFiled: June 12, 2015Date of Patent: March 29, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Yuan Chen, Yi-Tzu Chen, Hau-Tai Shieh, Tsung-yung Jonathan Chang
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Patent number: 9275721Abstract: Apparatus and methods for providing a high density memory array with reduced read access time are disclosed. Multiple split bit lines are arranged along columns of adjacent memory bit cells. A multiple input sense amplifier is coupled to the multiple split bit lines. The loading on the multiple split bit line is reduced, and the corresponding read speed of the memory array is enhanced over the prior art. The sense amplifier and the memory bit cells have a common cell pitch layout height so that no silicon area penalty arises due to the use of the multiple split bit lines and sense amplifiers. Increased memory array efficiency is achieved.Type: GrantFiled: July 30, 2010Date of Patent: March 1, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tzu Chen, Bin-Hau Lo, Tsai-Hsin Lai, Pey-Huey Chen, Hau-Tai Shieh
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Patent number: 9208857Abstract: An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer.Type: GrantFiled: April 30, 2014Date of Patent: December 8, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tzu Chen, Wei-jer Hsieh, Tsai-Hsin Lai, Ling-Fang Hsu, Hau-Tai Shieh
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Publication number: 20150279450Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.Type: ApplicationFiled: June 12, 2015Publication date: October 1, 2015Inventors: Chien-Yuan Chen, Yi-Tzu Chen, Hau-Tai Shieh, Tsung-yung Jonathan Chang
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Publication number: 20150243350Abstract: A sense amplifier circuit includes a pair of data lines, a pair of inverters, and a data line charging circuit. Each of the inverters is connected to a respective one of the data lines. The data line charging circuit includes a transistor. The transistor has a source/drain terminal connected to one of the data lines and a gate terminal connected to the other of the data lines.Type: ApplicationFiled: May 14, 2015Publication date: August 27, 2015Inventors: Chien-Yuan Chen, HAU-TAI SHIEH
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Publication number: 20150235675Abstract: A circuit comprises a first transistor and a second transistor in a strap cell region between a first memory array and a second memory array of a memory device. The first transistor includes a first node connected to a first data line, and a second node connected to a second data line. The first node and the second node of the first transistor are complementary to each other in voltage level. Further, the second transistor includes a first node connected to the second data line, and a second node connected to the first data line. The first node and the second node of the second transistor are complementary to each other in voltage level.Type: ApplicationFiled: February 17, 2014Publication date: August 20, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: HUA-HSIN YU, HSIU FEN PENG, HAU-TAI SHIEH
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Patent number: 9058899Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.Type: GrantFiled: November 18, 2013Date of Patent: June 16, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Yuan Chen, Yi-Tzu Chen, Hau-Tai Shieh, Tsung-Yung Jonathan Chang
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Publication number: 20150162052Abstract: Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell.Type: ApplicationFiled: December 5, 2013Publication date: June 11, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: CHIEN-YU HUANG, CHIEN-YUAN CHEN, HAU-TAI SHIEH
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Publication number: 20150146480Abstract: Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.Type: ApplicationFiled: November 22, 2013Publication date: May 28, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: CHIEN-YUAN CHEN, CHIEN-YU HUANG, HAU-TAI SHIEH