Patents by Inventor Hau Thien Tran

Hau Thien Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100220804
    Abstract: A method for asymmetrical MIMO wireless communication begins by determining a number of transmission antennas for the asymmetrical MIMO wireless communication. The method continues by determining a number of reception antennas for the asymmetrical MIMO wireless communication. The method continues by, when the number of transmission antennas exceeds the number of reception antennas, using spatial time block coding for the asymmetrical MIMO wireless communication. The method continues by, when the number of transmission antennas does not exceed the number of reception antennas, using spatial multiplexing for the asymmetrical MIMO wireless communication.
    Type: Application
    Filed: May 20, 2010
    Publication date: September 2, 2010
    Applicant: BROADCOM CORPORATION
    Inventors: Christopher J. Hansen, Jason A. Trachewsky, Nambirajan Seshadri, Kelly Brian Cameron, Hau Thien Tran, Ba-Zhong Shen
  • Patent number: 7746886
    Abstract: A method for asymmetrical MIMO wireless communication begins by determining a number of transmission antennas for the asymmetrical MIMO wireless communication. The method continues by determining a number of reception antennas for the asymmetrical MIMO wireless communication. The method continues by, when the number of transmission antennas exceeds the number of reception antennas, using spatial time block coding for the asymmetrical MIMO wireless communication. The method continues by, when the number of transmission antennas does not exceed the number of reception antennas, using spatial multiplexing for the asymmetrical MIMO wireless communication.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: June 29, 2010
    Assignee: Broadcom Corporation
    Inventors: Christopher J. Hansen, Jason A. Trachewsky, Nambirajan Seshadri, Kelly Brian Cameron, Hau Thien Tran, Ba-Zhong Shen
  • Publication number: 20100138721
    Abstract: Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder. Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.
    Type: Application
    Filed: January 1, 2010
    Publication date: June 3, 2010
    Applicant: BROADCOM CORPORATION
    Inventors: Hau Thien Tran, Kelly Brian Cameron, Ba-Zhong Shen, Tak K. Lee
  • Patent number: 7715503
    Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: May 11, 2010
    Assignee: Broadcom Corporation
    Inventors: Kelly B. Cameron, Hau Thien Tran, Ba-Zhong Shen, Christopher R. Jones
  • Publication number: 20100077282
    Abstract: True bit level decoding of TTCM (Turbo Trellis Coded Modulation) of variable rates and signal constellations. A decoding approach is presented that allows for decoding on a bit level basis that allows for discrimination of the individual bits of a symbol. Whereas prior art approaches typically perform decoding on a symbol level basis, this decoding approach allows for an improved approach in which the hard decisions/best estimates may be made individually for each of the individual bits of an information symbol. In addition, the decoding approach allows for a reduction in the total number of calculations that need to be performed as well as the total number of values that need to be stored during the iterative decoding. The bit level decoding approach is also able to decode a signal whose code rate and/or signal constellation type (and mapping) may vary on a symbol by symbol basis.
    Type: Application
    Filed: November 30, 2009
    Publication date: March 25, 2010
    Applicant: BROADCOM CORPORATION
    Inventors: Ba-Zhong Shen, Kelly Brian Cameron, Hau Thien Tran
  • Patent number: 7661055
    Abstract: Partial-parallel implementation of LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a selected number of cycles is performed during each of bit node processing and check node processing when performing error correction decoding of an LDPC coded signal. The number of cycles of each of bit node processing and check node processing need not be the same. At least one functional block, component, portion of hardware, or calculation can be used during both of the bit node processing and check node processing thereby conserving space with an efficient use of processing resources. At a minimum, a semi-parallel approach can be performed where 2 cycles are performed during each of bit node processing and check node processing. Alternatively, more than 2 cycles can be performed for each of bit node processing and check node processing.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: February 9, 2010
    Assignee: Broadcom Corporation
    Inventors: Tak K. Lee, Hau Thien Tran, Ba-Zhong Shen, Kelly Brian Cameron
  • Patent number: 7657822
    Abstract: True bit level decoding of TTCM (Turbo Trellis Coded Modulation) of variable rates and signal constellations. A decoding approach is presented that allows for decoding on a bit level basis that allows for discrimination of the individual bits of a symbol. Whereas prior art approaches typically perform decoding on a symbol level basis, this decoding approach allows for an improved approach in which the hard decisions/best estimates may be made individually for each of the individual bits of an information symbol. In addition, the decoding approach allows for a reduction in the total number of calculations that need to be performed as well as the total number of values that need to be stored during the iterative decoding. The bit level decoding approach is also able to decode a signal whose code rate and/or signal constellation type (and mapping) may vary on a symbol by symbol basis.
    Type: Grant
    Filed: May 1, 2003
    Date of Patent: February 2, 2010
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Kelly Brian Cameron, Hau Thien Tran
  • Patent number: 7644339
    Abstract: Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: January 5, 2010
    Assignee: Broadcom Corporation
    Inventors: Hau Thien Tran, Kelly Brian Cameron, Ba-Zhong Shen, Tak K. Lee
  • Publication number: 20090327847
    Abstract: LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).
    Type: Application
    Filed: July 31, 2009
    Publication date: December 31, 2009
    Applicant: BROADCOM CORPORATION
    Inventors: Ba-Zhong Shen, Hau Thien Tran, Tak K. Lee, Kelly Brian Cameron
  • Publication number: 20090285320
    Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed.
    Type: Application
    Filed: August 3, 2009
    Publication date: November 19, 2009
    Applicant: BROADCOM CORPORATION
    Inventors: Kelly B. Cameron, Hau Thien Tran, Ba-Zhong Shen, Christopher R. Jones
  • Patent number: 7617433
    Abstract: Implementation of LDPC (Low Density Parity Check) decoder by sweeping through sub-matrices. A novel approach is presented by which an LDPC coded signal is decoded processing the columns and rows of the individual sub-matrices of the low density parity check matrix corresponding to the LDPC code. The low density parity check matrix can partitioned into rows and columns according to each of the sub-matrices of it, and each of those sub-matrices also includes corresponding rows and columns. For example, when performing bit node processing, the same columns of at 1 or more sub-matrices can be processed together (e.g., all 1st columns in 1 or more sub-matrices, all 2nd columns in 1 or more sub-matrices, etc.). Analogously, when performing check node processing, the same rows of 1 or more sub-matrices can be processed together (e.g., all 1st rows in 1 or more sub-matrices, all 2nd rows in 1 or more sub-matrices, etc.).
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: November 10, 2009
    Assignee: Broadcom Corporation
    Inventors: Tak K. Lee, Hau Thien Tran, Ba-Zhong Shen, Kelly Brian Cameron
  • Patent number: 7617442
    Abstract: Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero element positions within the parity check matrix (or its corresponding sub-matrices). When designing an LDPC code, this approach is efficient to find and avoid cycles (or loops) in the LDPC code's corresponding bipartite graph. Another approach involves GRS (Generalized Reed-Solomon) code based LDPC code construction. These LDPC codes can be implemented in a wide variety of communication devices, including those implemented in wireless communication systems that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: November 10, 2009
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Tak K. Lee, Kelly Brian Cameron, Hau Thien Tran
  • Patent number: 7617441
    Abstract: Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero element positions within the parity check matrix (or its corresponding sub-matrices). When designing an LDPC code, this approach is efficient to find and avoid cycles (or loops) in the LDPC code's corresponding bipartite graph. Another approach involves GRS (Generalized Reed-Solomon) code based LDPC code construction. These LDPC codes can be implemented in a wide variety of communication devices, including those implemented in wireless communication systems that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: November 10, 2009
    Assignee: Broadcom Corporation
    Inventors: Tak K. Lee, Ba-Zhong Shen, Kelly Brian Cameron, Hau Thien Tran
  • Patent number: 7600180
    Abstract: Iterative metric updating when decoding LDPC (Low Density Parity Check) coded signals and LDPC coded modulation signals. A novel approach is presented for updating the bit metrics employed when performing iterative decoding of LDPC coded signals. This bit metric updating is also applicable to decoding of signals that have been generated using combined LDPC coding and modulation encoding to generate LDPC coded modulation signals. In addition, the bit metric updating is also extendible to decoding of LDPC variable code rate and/or variable modulation signals whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. By ensuring that the bit metrics are updated during the various iterations of the iterative decoding processing, a higher performance can be achieved than when the bit metrics remain as fixed values during the iterative decoding processing.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: October 6, 2009
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Hau Thien Tran, Kelly Brian Cameron
  • Patent number: 7587659
    Abstract: Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders. A novel approach is presented by which the front end design of device capable to decode LDPC coded signals facilitates parallel decoding processing of the LDPC coded signal. The implementation of the front end memory management in conjunction with the implementation of a metric generator operate cooperatively lend themselves for very efficient parallel decoding processing of LDPC coded signals. There are several embodiments by which the front end memory management and the metric generator may be implemented to facilitate this parallel decoding processing of LDPC coded signals. This also allows for the decoding of variable code rate and/or variable modulation signals whose code rate and/or modulation varies as frequently as on a block by block basis (e.g., a block may include a group of symbols within a frame).
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: September 8, 2009
    Assignee: Broadcom Corporation
    Inventors: Hau Thien Tran, Kelly Brian Cameron, Ba-Zhong Shen
  • Publication number: 20090217142
    Abstract: Rate control adaptable communications. A common trellis is employed at both ends of a communication system (in an encoder and decoder) to code and decode data at different rates. The encoding employs a single encoder whose output bits may be selectively punctured to support multiple modulations (constellations and mappings) according to a rate control sequence. A single decoder is operable to decode each of the various rates at which the data is encoded by the encoder. The rate control sequence may include a number of rate controls arranged in a period that is repeated during encoding and decoding. Either one or both of the encoder and decoder may adaptively select a new rate control sequence based on a variety of operational parameters including operating conditions of the communication system, a change in signal to noise ratio (SNR), etc.
    Type: Application
    Filed: May 9, 2009
    Publication date: August 27, 2009
    Applicant: BROADCOM CORPORATION
    Inventors: Kelly Brian Cameron, Ba-Zhong Shen, Hau Thien Tran
  • Patent number: 7570700
    Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo?N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: August 4, 2009
    Assignee: Broadcom Corporation
    Inventors: Kelly B. Cameron, Hau Thien Tran, Ba-Zhong Shen, Christopher R. Jones
  • Publication number: 20090193312
    Abstract: Fixed-spacing parity insertion for FEC (Forward Error Correction) codewords. Fixed spacing is employed to intersperse parity bits among information bits when generating a codeword. According to this fixed spacing, a same number of information bits is placed between each of the parity bits within the codeword. If desired, the order of the parity bits may be changed before they are placed into the codeword. Moreover, the order of the information bits may also be modified before they are placed into the codeword. The FEC encoding employed to generate the parity bits from the information bits can be any of a variety of codes include Reed-Solomon (RS) code, LDPC (Low Density Parity Check) code, turbo code, turbo trellis coded modulation (TTCM), or some other code providing FEC capabilities.
    Type: Application
    Filed: January 29, 2008
    Publication date: July 30, 2009
    Applicant: Broadcom Corporation
    Inventors: Tak K. Lee, Ba-Zhong Shen, Hau Thien Tran, Kelly Brian Cameron
  • Publication number: 20090187804
    Abstract: LDPC (Low Density Parity Check) coding and interleaving implemented in multiple-input-multiple-output (MIMO) communication systems. As described herein, a wide variety of irregular LDPC codes may be generated using GRS or RS codes. A variety of communication device types are also presented that may employ the error correcting coding (ECC) using a GRS-based irregular LDPC code, along with appropriately selected interleaving, to provide for communications using ECC. These communication devices may be implemented to in wireless communication systems including those that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.11 TGn (High Throughput)).
    Type: Application
    Filed: March 28, 2009
    Publication date: July 23, 2009
    Applicant: BROADCOM CORPORATION
    Inventors: Ba-Zhong Shen, Christopher J. Hansen, Joseph Paul Lauer, Kelly Brian Cameron, Tak K. Lee, Hau Thien Tran
  • Patent number: 7559010
    Abstract: A short length LDPC (Low Density Parity Check) code and modulation adapted for high speed Ethernet applications. In some instances, the short length LDPC code and modulation may be employed within the recommended practices currently being developed by the IEEE 802.3an (10GBASE-T) Task Force. The IEEE 802.3an (10GBASE-T) Task Force has been commissioned to develop and standardize communications protocol adapted particularly for Ethernet operation over 4 wire twisted pair cables. A new LDPC code, some possible embodiments of constellations and the corresponding mappings, as well as possible embodiments of various parity check matrices, H, of the LDPC code are presented herein to provide for better overall performance than other proposed LDPC codes existent in the art of high speed Ethernet applications. Moreover, this proposed LDPC code may be decoded using a communication device having much less complexity than required to decode other proposed LDPC codes existent in this technology space.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: July 7, 2009
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Kelly Brian Cameron, Hau Thien Tran, Scott Richard Powell