Patents by Inventor Hau Thien Tran

Hau Thien Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7409006
    Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: August 5, 2008
    Assignee: Broadcom Corporation
    Inventors: Kelly Brian Cameron, Ba-Zhong Shen, Hau Thien Tran, Christopher R. Jones, Thomas A. Hughes, Jr.
  • Patent number: 7406650
    Abstract: Variable code rate and signal constellation turbo trellis coded modulation (TTCM) codec. The decoding can be performed on signals whose various symbols have been mapped to multiple modulations (constellations and mappings) according to a rate control sequence. The rate control sequence may include a number of rate controls arranged in a period that is repeated during encoding to generate the signal that is subsequently decoded. Either one or both of an encoder that generates the signal and a decoder that decodes the signal may adaptively select a new rate control sequence based on operating conditions of the communication system, such as a change in signal to noise ratio (SNR).
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: July 29, 2008
    Assignee: Broadcom Corporation
    Inventors: Kelly Brian Cameron, Ba-Zhong Shen, Hau Thien Tran
  • Patent number: 7401283
    Abstract: Amplifying magnitude metric of received signals during iterative decoding of LDPC code and LDPC coded modulation. By appropriately selecting a metric coefficient value that is used to calculate the initial conditions when decoding LDPC coded signals, a significant reduction in BER may be achieved at certain SNRs. The appropriate selection of the metric coefficient value may be performed depending on the particular SNR at which a communication system is operating. By adjusting this metric coefficient value according to the given LDPC code, modulation, and noise variance, the overall performance of the decoding may be significantly improved. The convergence speed is slowed down so that the decoder will not go to the wrong codeword, and the moving range of the outputs of the decoder is restricted so that the output will not oscillate too much and will eventually move to the correct codeword.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: July 15, 2008
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Kelly Brian Cameron, Scott Richard Powell, Hau Thien Tran
  • Patent number: 7395487
    Abstract: Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a decoder may use the same circuitry to perform updating of edge messages with respect to bit nodes as well as updating of edge messages with respect to check nodes in the context of decoding LDPC coded signals. In addition, several very efficient architectures are presented to performing check node processing that involves the updating of edge messages with respect to check nodes. One embodiment performs check node processing using min** (min-double-star) processing in conjunction with min**? (min-double-star-minus) processing. Another embodiment performs check node processing using min†† (min-double-dagger) processing in conjunction with min†? (min-dagger-minus) processing. In addition, a single FIFO may be implemented to service a number of macro blocks in a parallel decoding implementation.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: July 1, 2008
    Assignee: Broadcom Corporation
    Inventors: Hau Thien Tran, Kelly Brian Cameron, Ba-Zhong Shen
  • Patent number: 7383485
    Abstract: Fast min*? (min-star-minus) or max*? (max-star-minus) circuit in LDPC (Low Density Parity Check) decoder. A novel and efficient approach by which certain of the calculations required to perform check node processing within various types of decoders is presented. The functionality and architectures presented herein are applicable to LDPC decoders and may also be employed within other types of decoders that are operable to decode other types of coded signals as well. The parallel and sometimes simultaneous calculation and determination of certain parts of the overall resultant of the max*? and/or min*? processing allows for very fast operation when compared to prior art approaches.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: June 3, 2008
    Assignee: Broadcom Corporation
    Inventors: Hau Thien Tran, Kelly Brian Cameron, Ba-Zhong Shen
  • Patent number: 7383487
    Abstract: IPHD (Iterative Parallel Hybrid Decoding) of various MLC (Multi-Level Code) signals. Various embodiments are provided by which IPHD may be performed on MLC LDPC (Multi-Level Code Low Density Parity Check) coded modulation signals mapped using a plurality of mappings. This IPHD may also be performed on MLC LDPC coded modulation signals mapped using only a singe mapping as well. In addition, various embodiments are provided by which IPHD may be performed on ML TC (Multi-Level Turbo Code) signals. These principles of IPHD, shown with respect to various embodiments IPHD of MLC LDPC coded modulation signals as well as the IPHD of ML TC signals, may be extended to performing IPHD of other signal types as well. Generally speaking, based on the degree of the MLC signal, a corresponding number of parallel paths operate in cooperation to decode the various levels of the MLC signal.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: June 3, 2008
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Hau Thien Tran, Kelly Brian Cameron
  • Patent number: 7383493
    Abstract: LDPC (Low Density Parity Check) coded modulation hybrid decoding using non-Gray code maps for improved performance. Check node updating and symbol node updating are successively and alternatively performed on bit edge messages for a predetermined number of decoding iterations or until sufficient degree of precision is achieved. The symbol node updating of the bit edge messages uses symbol metrics corresponding to the symbol being decoded and the bit edge messages most recently updated by check node updating. The check node updating of the bit edge messages uses the bit edge messages most recently updated by symbol node updating. The symbol node updating computes possible soft symbol estimates. LDPC coded modulation hybrid decoding can decode an LDPC-BICM (Low Density Parity Check-Bit Interleaved Coded Modulation) signal having a symbol mapped using non-Gray code mapping. By using the non-Gray code mapping, a performance improvement is achieved over an only Gray code mapping system.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: June 3, 2008
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Hau Thien Tran, Kelly Brian Cameron
  • Patent number: 7370265
    Abstract: Bandwidth efficient coded modulation scheme based on MLC (Multi-Level Code) signals having multiple maps. The use of multiple maps is adapted to various types of coded signals including multi-level LDPC coded modulation signals and other MLC signals to provide for a significant performance gain in the continual effort trying to reach towards Shannon's limit. In the instance of LDPC coded signals, various level LDPC codewords (e.g., an MLC block) are generated from individual corresponding LDPC encoders. These various level LDPC codewords are arranged into a number of sub-blocks that corporately form an MLC block. Encoded bits from levels of the MLC block are arranged to form symbols that are mapped according to at least two modulations. Each modulation includes a constellation shape and a corresponding mapping. This use of multiple mappings provides for improved performance when compared to encoders that employ only a single mapping.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: May 6, 2008
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Hau Thien Tran, Kelly Brian Cameron
  • Patent number: 7360146
    Abstract: Inverse function of min*:min*? (inverse function of max*:max*?). Two new parameters are employed to provide for much improved decoding processing for codes that involve the determination of a log corrected minimal and/or a log corrected maximal value from among a number of possible values. Examples of some of the codes that may benefit from the improved decoding processing provided by the inverse function of min*:min*? (and/or inverse function of max*:max*?) include turbo coding, parallel concatenated trellis coded modulated (PC-TCM) code, turbo trellis coded modulated (TTCM) code, and low density parity check (LDPC) code among other types of codes. The total number of processing steps employed within the decoding of a signal is significantly reduced be employing the inverse function of min*:min*? (and/or inverse function of max*:max*?) processing.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: April 15, 2008
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Kelly Brian Cameron, Thomas A. Hughes, Jr., Hau Thien Tran
  • Publication number: 20080082868
    Abstract: Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.
    Type: Application
    Filed: February 21, 2007
    Publication date: April 3, 2008
    Applicant: Broadcom Corporation, a California Corporation
    Inventors: Hau Thien Tran, Kelly Brian Cameron, Ba-Zhong Shen, Tak K. Lee
  • Patent number: 7350130
    Abstract: Decoding LDPC (Low Density Parity Check) code with new operators based on min* operator. New approximate operators are provided that may be employed to assist in calculating one or a minimum value (or a maximum value) when decoding various coded signals. In the context of LDPC decoding that involves both bit node processing and check node processing, either of these new operators (i.e., the min† (min-dagger) operator or the min? (min-prime) operator) may be employed to perform the check node processing that involves updating the edge messages with respect to the check nodes. Either of these new operators, min† operator or min? operator, is shown herein to be a better approximate operator to the min** operator.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: March 25, 2008
    Assignee: Broadcom Corporation
    Inventors: Hau Thien Tran, Ba-Zhong Shen, Kelly Brian Cameron
  • Patent number: 7328398
    Abstract: Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are required to perform decoding of signals coded using LDPC code. These new parameters may be employed to provide for much improved decoding processing for LDPC codes when that decoding involves the determination of a minimal and/or maximal value, or a minimal and/or maximal log corrected value, from among a number of possible values. The total number of processing steps employed within the decoding of an LDPC-coded signal is significantly reduced be employing the min*, max*, min**, or max** (and their respective inverses) decoding processing described herein.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: February 5, 2008
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Kelly Brian Cameron, Hau Thien Tran
  • Patent number: 7321633
    Abstract: Determination of variable code rates for a rate control sequence. A rate control sequence governs symbols that are to be encoded and/or decoded. A different rate control value may be used to control code rates of individual symbols in a signal. The determination of the variable code rates may be performed based on a number of parameters including a communication system's operating conditions and/or the signal to noise ratio (SNR) of a communication channel. The variable code rates may also adaptively change, in real time (if desired), in response to the communication system's operating conditions including a communication channel's SNR. The variable code rate functionality may also be adaptively tailored to match the SNR of a communication receiver's communication channel within a multi-receiver communication system; those receivers in a beam spot (higher SNR) may operate using a higher code rate than those receivers further away from the spot (lower SNR).
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: January 22, 2008
    Assignee: Broadcom Corporation
    Inventors: Kelly Brian Cameron, Ba-Zhong Shen, Hau Thien Tran
  • Patent number: 7322005
    Abstract: LDPC (Low Density Parity Check) coded modulation symbol decoding using non-Gray code maps for improved performance. Symbol decoding is supported by appropriately modifying an LDPC tripartite graph to eliminate the bit nodes thereby generating an LDPC bipartite graph (such that symbol nodes are appropriately mapped directly to check nodes thereby obviating the bit nodes). The edges that communicatively couple the symbol nodes to the check nodes are labeled appropriately to support symbol decoding of the LDPC coded modulation signal. In addition, the LDPC coded modulation symbol decoding can be employed to decode a signal that has been encoded using LDPC-BICM (Low Density Parity Check-Bit Interleaved Coded Modulation) encoding with non-Gray code mapping. By using the non-Gray code mapping, a performance improvement over such a system using only Gray code mapping may be achieved.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: January 22, 2008
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Hau Thien Tran, Kelly Brian Cameron
  • Patent number: 7281192
    Abstract: LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node processing. This novel approach to decoding of LDPC coded signals may be described as being LDPC bit-check parallel decoding. In some alternative embodiment, the approach to decoding LDPC coded signals may be modified to LDPC symbol-check parallel decoding or LDPC hybrid-check parallel decoding. A novel approach is presented by which the edge messages with respect to the bit nodes and the edge messages with respect to the check nodes may be updated simultaneously and in parallel to one another. Appropriately constructed executing orders direct the sequence of simultaneous operation of updating the edge messages at both nodes types (e.g., edge and check). For various types of LDPC coded signals, including parallel-block LDPC coded signals, this approach can perform decoding processing in almost half of the time as provided by previous decoding approaches.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: October 9, 2007
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Hau Thien Tran, Kelly Brian Cameron
  • Patent number: 7243287
    Abstract: Decoding LDPC (Low Density Parity Check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph. A means for decoding LDPC coded signals is presented whereby edge messages may be updated using only multiplication (or log domain addition). By appropriate modification of the various calculations that need to be performed when updating edge messages, the calculations may be reduced to only performing product of terms functions. When implementing such functionality in hardware within a communication device that is operable to decode LDPC coded signals, this reduction in processing complexity greatly eases the actual hardware's complexity as well. A significant savings in processing resources, memory, memory management concerns, and other performance driving parameters may be made.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: July 10, 2007
    Assignee: Broadcom Corporation
    Inventors: Kelly Brian Cameron, Ba-Zhong Shen, Hau Thien Tran
  • Patent number: 7242726
    Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Soloman encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed.
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: July 10, 2007
    Assignee: Broadcom Corporation
    Inventors: Kelly B. Cameron, Ba-Zhong Shen, Hau Thien Tran, Christopher R. Jones, Thomas Ashford Hughes, Jr.
  • Patent number: 7221714
    Abstract: Non-systematic and non-linear PC-TCM (Parallel Concatenate Trellis Coded Modulation). A non-systematic and non-linear PC-TCM code is presented that provides quite comparable performance to turbo encoding using only systematic and linear trellis codes (e.g., convolutional codes). The non-systematic and non-linear PC-TCM described herein may be modified to support a wide variety of code rates (e.g., rate 2/3, 5/6, 8/9, and 3/4 among other rates) and also a wide modulation types (e.g., 8 PSK (8 Phase Shift Key) and 16 QAM (16 Quadrature Amplitude Modulation) among other modulation types). In one embodiment, a non-systematic and non-linear PC-TCM presented herein comes to within approximately 0.15 dB of a systematic and linear turbo code. A design approach is presented that allows for the design of such non-systematic and non-linear PC-TCM codes and several exemplary embodiments are also presented that have been designed according to these presented principles.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: May 22, 2007
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Kelly Brian Cameron, Hau Thien Tran, Christopher R. Jones
  • Patent number: 7216283
    Abstract: Iterative metric updating when decoding LDPC (Low Density Parity Check) coded signals and LDPC coded modulation signals. A novel approach is presented for updating the bit metrics employed when performing iterative decoding of LDPC coded signals. This bit metric updating is also applicable to decoding of signals that have been generated using combined LDPC coding and modulation encoding to generate LDPC coded modulation signals. In addition, the bit metric updating is also extendible to decoding of LDPC variable code rate and/or variable modulation signals whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. By ensuring that the bit metrics are updated during the various iterations of the iterative decoding processing, a higher performance can be achieved than when the bit metrics remain as fixed values during the iterative decoding processing.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: May 8, 2007
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Hau Thien Tran, Kelly Brian Cameron
  • Patent number: 7210092
    Abstract: Symbol by symbol variable constellation type and/or mapping capable communication device. A communication device is operable to perform processing of a variable constellation signal whose constellation varies on a symbol by symbol basis. This may involve performing encoding of input to generate the variable constellation signal; alternatively or in addition to, this may involve performing decoding of a variable constellation signal as well. In doing so, this approach may involve using a single encoder and/or decoder (depending on the application). In some instances, a single device is operable to encode a first variable constellation signal (for transmission to another device) and to decode a second variable constellation signal (that has been received from another device). In addition, a method of coding (including one or both of encoding and decoding) may also operate of a variable constellation signal whose constellation varies on a symbol by symbol basis.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: April 24, 2007
    Assignee: Broadcom Corporation
    Inventors: Kelly Brian Cameron, Ba-Zhong Shen, Hau Thien Tran