Patents by Inventor Hayato Okuda

Hayato Okuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9319128
    Abstract: A helicopter-mounted communication apparatus encodes video data at a compression rate based on a percentage of time a transmission beam is blocked by rotor blades. When a number of video packets is less than a specified number, the helicopter-mounted communication apparatus inserts null packets to keep a packet rate constant, then deletes the null packets and attaches additional information to another packet indicating the number of deleted null packets, and after buffering modulates and transmits a signal toward a communication satellite at transmittable-time points.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 19, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazushi Yamamoto, Yutaka Ozaki, Hayato Okuda
  • Publication number: 20150117303
    Abstract: A helicopter satellite communication system in which a terrestrial station communication apparatus communicates with a helicopter-mounted communication apparatus via a communication satellite. The terrestrial station communication apparatus includes: an encoder that performs error-correcting encoding of target transmission information; a packet interleaver that divides the encoded information into a plurality of packets and rearranges the packets; and a transmitter that transmits the rearranged packets to the helicopter-mounted communication apparatus. The helicopter-mounted communication apparatus includes: a receiver that receives the packets that are transmitted from the terrestrial station communication apparatus: a packet de-interleaver that rearranges the received packets in the original order; and a decoder that, by decoding the rearranged packets, restores the information that is lost due to the rotor blades of the helicopter.
    Type: Application
    Filed: March 18, 2013
    Publication date: April 30, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kazushi Yamamoto, Yutaka Ozaki, Hayato Okuda
  • Publication number: 20150055549
    Abstract: A helicopter-mounted communication apparatus encodes video data at a compression rate based on a percentage of time a transmission beam is blocked by rotor blades. When a number of video packets is less than a specified number, the helicopter-mounted communication apparatus inserts null packets to keep a packet rate constant, then deletes the null packets and attaches additional information to another packet indicating the number of deleted null packets, and after buffering modulates and transmits a signal toward a communication satellite at transmittable-time points.
    Type: Application
    Filed: March 18, 2013
    Publication date: February 26, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kazushi Yamamoto, Yutaka Ozaki, Hayato Okuda
  • Publication number: 20140170814
    Abstract: A semiconductor device includes: stacked semiconductor chips having respective input/output pads on surfaces thereof; a lower resin body molding the lower semiconductor chip and having a surface coplanar with the lower chip; an upper resin body molding the upper chip and coupled with the first resin body; wirings connected to input/output pads of the lower or upper chip and extending horizontally; external connection metal posts formed on the wirings and having tops exposed from the second resin body; and ball-shaped external connection terminals connected to the tops of the external connection metal posts.
    Type: Application
    Filed: February 19, 2014
    Publication date: June 19, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hayato OKUDA, Yasunori KAWAOKA, Akira TAKASHIMA
  • Publication number: 20140061887
    Abstract: A semiconductor device includes: a plurality of semiconductor chips to be mutually bonded via a bonding resin; a sealing resin to seal the plurality of semiconductor chips; and an anchor to be disposed in a first semiconductor chip included by the plurality of semiconductor chips and to seize the bonding resin.
    Type: Application
    Filed: August 20, 2013
    Publication date: March 6, 2014
    Applicant: Fujitsu Semiconductor Limited
    Inventors: Hayato OKUDA, Yoshikazu KUMAGAYA
  • Publication number: 20120104606
    Abstract: A semiconductor device includes: stacked semiconductor chips having respective input/output pads on surfaces thereof; a lower resin body molding the lower semiconductor chip and having a surface coplanar with the lower chip; an upper resin body molding the upper chip and coupled with the first resin body; wirings connected to input/output pads of the lower or upper chip and extending horizontally; external connection metal posts formed on the wirings and having tops exposed from the second resin body; and ball-shaped external connection terminals connected to the tops of the external connection metal posts.
    Type: Application
    Filed: August 25, 2011
    Publication date: May 3, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hayato OKUDA, Yasunori Kawaoka, Akira Takashima
  • Publication number: 20110239034
    Abstract: There is provided a transmission apparatus including: a clock generator; a first circuit including first data processors to process input data based on a first input clock, the first data processors electrically connected in series each transmitting data processed thereby and the first input clock to the next first data processor, the first input clock of the beginning first data processor being one of the clocks generated by the clock generator; a second circuit including: second data processors same as the first data processors; and phase adjusters each to adjust a phase of the second input clock and transmitting the second input clock adjusted thereby to the next second data processor; phase comparators each to compare phases of the first input clock and the second input clock; and a delay controller to control the phase adjusters, based on comparison results of the phase comparators.
    Type: Application
    Filed: March 3, 2011
    Publication date: September 29, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Hayato OKUDA
  • Patent number: 7800421
    Abstract: An apparatus includes plural combinations of a clock supplier and a clock supply destination supplied with a clock from the clock supplier. The clock supply destination includes a return route through which the clock supply destination returns a clock to a corresponding clock supplier. The clock supplier includes a variable delay unit that adds a delay to the clock to be supplied to a corresponding clock supply destination; a comparison-reference-clock supply unit that supplies a comparison reference clock having the same phase as that of a comparison reference clock supplied from other clock supplier; a phase comparator that compares the phase of a return clock returned from a corresponding clock supply destination with that of the comparison reference clock; and a phase-difference control unit that controls the delay, so that the phases of the return clock and the comparison reference clock coincide with each other, based on the comparison result.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: September 21, 2010
    Assignee: Fujitsu Limited
    Inventors: Hayato Okuda, Hiroyuki Matsuo
  • Publication number: 20080122503
    Abstract: An apparatus includes plural combinations of a clock supplier and a clock supply destination supplied with a clock from the clock supplier. The clock supply destination includes a return route through which the clock supply destination returns a clock to a corresponding clock supplier. The clock supplier includes a variable delay unit that adds a delay to the clock to be supplied to a corresponding clock supply destination; a comparison-reference-clock supply unit that supplies a comparison reference clock having the same phase as that of a comparison reference clock supplied from other clock supplier; a phase comparator that compares the phase of a return clock returned from a corresponding clock supply destination with that of the comparison reference clock; and a phase-difference control unit that controls the delay, so that the phases of the return clock and the comparison reference clock coincide with each other, based on the comparison result.
    Type: Application
    Filed: November 27, 2007
    Publication date: May 29, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Hayato Okuda, Hiroyuki Matsuo
  • Patent number: 6621169
    Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: September 16, 2003
    Assignee: Fujitsu Limited
    Inventors: Katsuhito Kikuma, Mitsutaka Ikeda, Yoshihiro Tsukidate, Yuji Akashi, Kaname Ozawa, Akira Takashima, Tadashi Uno, Takao Nishimura, Fumihiko Ando, Hiroshi Onodera, Hayato Okuda
  • Publication number: 20020027295
    Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.
    Type: Application
    Filed: August 29, 2001
    Publication date: March 7, 2002
    Applicant: Fujitsu Limited
    Inventors: Katsuhito Kikuma, Mitsutaka Ikeda, Yoshihiro Tsukidate, Yuji Akashi, Kaname Ozawa, Akira Takashima, Tadashi Uno, Takao Nishimura, Fumihiko Ando, Hiroshi Onodera, Hayato Okuda
  • Patent number: 6316838
    Abstract: A semiconductor device includes a substrate provided with a plurality of leads, a face-down semiconductor element provided on one surface of the substrate, a first stacked semiconductor element and a second stacked semiconductor element provided on another surface of the substrate and connected to the substrate by wires, and an extended wiring mechanism for connecting electrodes of the face-down semiconductor element and electrodes of the first and second semiconductor elements. The connected electrodes are equi-electrodes whose electrical characteristics are equal.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: November 13, 2001
    Assignee: Fujitsu Limited
    Inventors: Kaname Ozawa, Hayato Okuda, Tetsuya Hiraoka, Mitsutaka Sato, Yuji Akashi, Akira Okada, Masahiko Harayama
  • Patent number: 6215182
    Abstract: A semiconductor device includes the first through third semiconductor devices which are stacked on a substrate and the first through third wires for connecting the semiconductor elements and the substrate. The first wires serve to connect electrodes of the first semiconductor element positioned uppermost and electrodes of the second semiconductor element. The second wires serve to connect the electrodes of the second semiconductor element and electrodes of the third semiconductor element. The third wires serve to connect the electrodes of the third semiconductor element and bonding pads of the substrate. Between the first wires and the electrodes of the second semiconductor element and between the second wires and the electrodes of the third semiconductor element, stud bumps are provided so as to form space therebetween, thereby avoiding short-circuits therebetween.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: April 10, 2001
    Assignee: Fujitsu Limited
    Inventors: Kaname Ozawa, Hayato Okuda, Ryuji Nomoto, Yuji Akashi, Katsuro Hiraiwa
  • Patent number: 5865496
    Abstract: A door structure of a motor vehicle has an inner panel and an outer panel. The door structure includes an impact load absorber member, provided at an outer panel side of the door, for absorbing and reducing a side collision impact load acting on a passenger by contact with the passenger. An opening is provided in the inner panel for allowing at least one portion of the impact load absorber member to enter. An passenger is compartment of the vehicle during a side collision. A supporting device is provided in the door for supporting the impact load absorber member.
    Type: Grant
    Filed: October 7, 1996
    Date of Patent: February 2, 1999
    Assignee: Mazda Motor Corporation
    Inventors: Seiji Odan, Hayato Okuda, Kuniaki Ishigami