Patents by Inventor Heather L. Hanson

Heather L. Hanson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7890831
    Abstract: A system and method for testing a processor. The system includes a gold processor and a test processor, wherein the test processor is the device under test (DUT). The test processor and the gold processor are identical. A first memory is coupled to the gold processor by a first memory bus and a second memory, independent of the first, is coupled to the test processor by a second memory bus. The first and second memories are identical. A memory bus comparator coupled to the first and second memory buses compares memory bus signals generated by the gold and test processors, and selectively provide a first indication if a mismatch occurs. A peripheral bus comparator is also coupled to the gold and test processors, and compares downstream transactions generated by the gold and test processors and to provide a second indication if a peripheral bus comparison results in a mismatch.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: February 15, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Michael L. Choate, Mark D. Nicol, Heather L. Hanson, Michael J. Borsch, Arthur M. Ryan, Chandrakant Pandya
  • Publication number: 20100332872
    Abstract: A mechanism is provided for priority-based power capping. A power management controller identifies a set of priorities for a set of partitions of the data processing system. The power management controller determines whether a measured power of the data processing system exceeds a power cap for the data processing system. Responsive to the measured power exceeding the power cap, the power management controller sends a set of commands to a set of component actuators to adjust one or more of a set of operation parameters for a set of components associated with the set of partitions using the set of priorities. The set of component actuators adjust the one or more of the set of operational parameters associated with the set of component in order to reduce a power consumption of the data processing system.
    Type: Application
    Filed: June 30, 2009
    Publication date: December 30, 2010
    Applicant: International Business Machines Corporation
    Inventors: Heather L. Hanson, Charles Robert Lefurgy, Karthick Rajamani, Freeman L. Rawson, III, Malcolm S. Ware
  • Publication number: 20100146316
    Abstract: A method, system, and computer program product for optimizing power consumption of an executing processor executing. The method includes determining a first sensitivity relationship (SR) based on a first and a second performance metric value (PMV) measured at a first and second operating frequency (OF), respectively. The first SR predicts workload performance over a range of OFs. A third OF is determined based on the first SR and a specified workload performance floor. A third PMV is measured by executing the processor operating at the third OF. A second SR based on the second and third PMVs is then determined. The first and second SRs are logically combined to generate a third SR. Based on the third SR, a fourth OF is outputted.
    Type: Application
    Filed: December 8, 2008
    Publication date: June 10, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John B. Carter, Heather L. Hanson, Karthick Rajamani, Freeman L. Rawson, III, Malcolm S. Ware
  • Publication number: 20090307549
    Abstract: A system and method for testing a processor. The system includes a gold processor and a test processor, wherein the test processor is the device under test (DUT). The test processor and the gold processor are identical. A first memory is coupled to the gold processor by a first memory bus and a second memory, independent of the first, is coupled to the test processor by a second memory bus. The first and second memories are identical. A memory bus comparator coupled to the first and second memory buses compares memory bus signals generated by the gold and test processors, and selectively provide a first indication if a mismatch occurs. A peripheral bus comparator is also coupled to the gold and test processors, and compares downstream transactions generated by the gold and test processors and to provide a second indication if a peripheral bus comparison results in a mismatch.
    Type: Application
    Filed: June 10, 2008
    Publication date: December 10, 2009
    Inventors: Michael L. Choate, Mark D. Nicol, Heather L. Hanson, Michael J. Borsch, Arthur M. Ryan, Chandrakant Pandya
  • Patent number: 6950904
    Abstract: A cache way replacement technique to identify and replace a least-recently used cache way. A cache way replacement technique in which a least-recently used cache way is identified and replaced, such that the replacement of cache ways over time is substantially evenly distributed among a set of cache ways in a cache memory. A least-recently used cache way is identified in a cache memory having a non-binary number of cache ways.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: September 27, 2005
    Assignee: Intel Corporation
    Inventors: Todd D. Erdner, Bradley G. Burgess, Heather L. Hanson
  • Publication number: 20030236948
    Abstract: A cache way replacement technique to identify and replace a least-recently used cache way. A cache way replacement technique in which a least-recently used cache way is identified and replaced, such that the replacement of cache ways over time is substantially evenly distributed among a set of cache ways in a cache memory. A least-recently used cache way is identified in a cache memory having a non-binary number of cache ways.
    Type: Application
    Filed: June 25, 2002
    Publication date: December 25, 2003
    Inventors: Todd D. Erdner, Bradley G. Burgess, Heather L. Hanson