Patents by Inventor Hee Joung PARK

Hee Joung PARK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11114163
    Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: September 7, 2021
    Assignee: SK hynix Inc.
    Inventors: Hee Joung Park, Kyeong Seung Kang, Won Chul Shin
  • Publication number: 20210165603
    Abstract: A method for operating a memory device includes providing a memory block including at least one source select transistor coupled between a source line and a bit line, a plurality of memory cells, and a drain select transistor, controlling a source select line coupled to the at least one source select transistor and a plurality of word lines coupled to the plurality of memory cells to be in a floating state, and applying an erase voltage to the source line and the bit line.
    Type: Application
    Filed: February 11, 2021
    Publication date: June 3, 2021
    Applicant: SK hynix Inc.
    Inventors: Byung In LEE, Hee Joung PARK, Keon Soo SHIM, Sang Heon LEE, Jae Il TAK
  • Patent number: 10950306
    Abstract: A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: March 16, 2021
    Assignee: SK hynix Inc.
    Inventors: Byung In Lee, Hee Joung Park, Keon Soo Shim, Sang Heon Lee, Jae Il Tak
  • Publication number: 20200294597
    Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.
    Type: Application
    Filed: June 3, 2020
    Publication date: September 17, 2020
    Applicant: SK hynix Inc.
    Inventors: Hee Joung PARK, Kyeong Seung KANG, Won Chul SHIN
  • Publication number: 20200294596
    Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.
    Type: Application
    Filed: June 3, 2020
    Publication date: September 17, 2020
    Applicant: SK hynix Inc.
    Inventors: Hee Joung PARK, Kyeong Seung KANG, Won Chul SHIN
  • Patent number: 10706929
    Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: July 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Hee Joung Park, Kyeong Seung Kang, Won Chul Shin
  • Publication number: 20200211650
    Abstract: A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.
    Type: Application
    Filed: July 12, 2019
    Publication date: July 2, 2020
    Applicant: SK hynix Inc.
    Inventors: Byung In LEE, Hee Joung PARK, Keon Soo SHIM, Sang Heon LEE, Jae Il TAK
  • Patent number: 10304544
    Abstract: A memory device includes a plurality of memory cells, bit lines connected to the plurality of memory cells, and page buffers coupled to the plurality of memory cells through the bit lines, and performing a read operation on the plurality of memory cells, wherein each of the page buffers comprises: a first latch controlling a bit line precharge operation during the read operation; and a second latch storing a result of a first sensing operation and a result of a second sensing operation performed after the first sensing operation, wherein a value stored in the second latch is inverted when the result of the first sensing operation and the result of second sensing operation are different from each other during the second sensing operation.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: May 28, 2019
    Assignee: SK hynix Inc.
    Inventors: Hee Joung Park, Kyeong Seung Kang, Won Chul Shin, Dong Hyuk Chae
  • Publication number: 20190043584
    Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.
    Type: Application
    Filed: March 23, 2018
    Publication date: February 7, 2019
    Applicant: SK hynix Inc.
    Inventors: Hee Joung PARK, Kyeong Seung KANG, Won Chul SHIN
  • Publication number: 20180322929
    Abstract: A memory device includes a plurality of memory cells, bit lines connected to the plurality of memory cells, and page buffers coupled to the plurality of memory cells through the bit lines, and performing a read operation on the plurality of memory cells, wherein each of the page buffers comprises: a first latch controlling a bit line precharge operation during the read operation; and a second latch storing a result of a first sensing operation and a result of a second sensing operation performed after the first sensing operation, wherein a value stored in the second latch is inverted when the result of the first sensing operation and the result of second sensing operation are different from each other during the second sensing operation.
    Type: Application
    Filed: December 8, 2017
    Publication date: November 8, 2018
    Inventors: Hee Joung PARK, Kyeong Seung KANG, Won Chul SHIN, Dong Hyuk CHAE
  • Patent number: 9965388
    Abstract: A memory device includes a memory cell array, a plurality of bit lines, and a plurality of page buffers including a plurality of cache latches, exchanging data with the memory cell array through the plurality of bit lines, wherein the plurality of cache latches are arranged in a column direction in parallel with the plurality of bit lines and a row direction perpendicular to the plurality of bit lines, and have a two-dimensional arrangement of M stages in the column direction, where M is a positive integer not corresponding to 2L and L is zero or a natural number.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: May 8, 2018
    Assignee: SK Hynix Inc.
    Inventors: Ki Chang Chun, Hee Joung Park, Tae Seung Shin, Sung Lae Oh
  • Publication number: 20170337130
    Abstract: A memory device includes a memory cell array, a plurality of bit lines, and a plurality of page buffers including a plurality of cache latches, exchanging data with the memory cell array through the plurality of bit lines, wherein the plurality of cache latches are arranged in a column direction in parallel with the plurality of bit lines and a row direction perpendicular to the plurality of bit lines, and have a two-dimensional arrangement of M stages in the column direction, where M is a positive integer not corresponding to 2L and L is zero or a natural number.
    Type: Application
    Filed: January 4, 2017
    Publication date: November 23, 2017
    Inventors: Ki Chang CHUN, Hee Joung PARK, Tae Seung SHIN, Sung Lae OH