Patents by Inventor Heinrich Koerner

Heinrich Koerner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10672678
    Abstract: In various embodiments, methods for forming a chip package are provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: June 2, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Heinrich Koerner, Michael Bauer, Reimund Engl, Michael Huettinger, Werner Kanert, Joachim Mahler, Brigitte Ruehle
  • Publication number: 20200013749
    Abstract: In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.
    Type: Application
    Filed: September 17, 2019
    Publication date: January 9, 2020
    Inventors: Joachim Mahler, Michael Bauer, Jochen Dangelmaier, Reimund Engl, Johann Gatterbauer, Frank Hille, Michael Huettinger, Werner Kanert, Heinrich Koerner, Brigitte Ruehle, Francisco Javier Santos Rodriguez, Antonio Vellei
  • Patent number: 10497634
    Abstract: In various embodiments, a chip package is provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: December 3, 2019
    Assignee: Infineon Technologies AG
    Inventors: Heinrich Koerner, Michael Bauer, Reimund Engl, Michael Huettinger, Werner Kanert, Joachim Mahler, Brigitte Ruehle
  • Patent number: 10461056
    Abstract: In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: October 29, 2019
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Michael Bauer, Jochen Dangelmaier, Reimund Engl, Johann Gatterbauer, Frank Hille, Michael Huettinger, Werner Kanert, Heinrich Koerner, Brigitte Ruehle, Francisco Javier Santos Rodriguez, Antonio Vellei
  • Publication number: 20190287875
    Abstract: In various embodiments, methods for forming a chip package are provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.
    Type: Application
    Filed: June 5, 2019
    Publication date: September 19, 2019
    Inventors: Heinrich Koerner, Michael Bauer, Reimund ENGL, Michael Huettinger, Werner Kanert, Joachim Mahler, Brigitte Ruehle
  • Patent number: 9941181
    Abstract: In various embodiments, a chip package is provided. The chip package may include a chip including a chip metal surface, a metal contact structure electrically contacting the chip metal surface, and packaging material including a contact layer being in physical contact with the chip metal surface and/or with the metal contact structure; wherein at least in the contact layer of the packaging material, a summed concentration of chemically reactive sulfur, chemically reactive selenium and chemically reactive tellurium is less than 10 atomic parts per million.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: April 10, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Heinrich Koerner, Michael Bauer, Reimund Engl, Michael Huettinger, Werner Kanert, Joachim Mahler, Brigitte Ruehle
  • Publication number: 20180061742
    Abstract: A semiconductor device includes an electrically conductive contact pad structure. Moreover, the semiconductor device includes a bond structure. The bond structure is in contact with the electrically conductive contact pad structure at least at an enclosed interface region. Additionally, the semiconductor device includes a degradation prevention structure laterally surrounding the enclosed interface region. The degradation prevention structure is vertically located between a portion of the bond structure and a portion of the electrically conductive contact pad structure.
    Type: Application
    Filed: August 24, 2017
    Publication date: March 1, 2018
    Inventors: Sergey Ananiev, Robert Bauer, Heinrich Koerner, Yik Yee Tan, Juergen Walter
  • Publication number: 20170338165
    Abstract: In various embodiments, a chip package is provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.
    Type: Application
    Filed: May 22, 2017
    Publication date: November 23, 2017
    Inventors: Heinrich KOERNER, Michael BAUER, Reimund ENGL, Michael HUETTINGER, Werner KANERT, Joachim MAHLER, Brigitte RUEHLE
  • Publication number: 20170338164
    Abstract: In various embodiments, a chip package is provided. The chip package may include a chip including a chip metal surface, a metal contact structure electrically contacting the chip metal surface, and packaging material including a contact layer being in physical contact with the chip metal surface and/or with the metal contact structure; wherein at least in the contact layer of the packaging material, a summed concentration of chemically reactive sulfur, chemically reactive selenium and chemically reactive tellurium is less than 10 atomic parts per million.
    Type: Application
    Filed: May 19, 2017
    Publication date: November 23, 2017
    Inventors: Heinrich Koerner, Michael Bauer, Reimund Engl, Michael Huettinger, Werner Kanert, Joachim Mahler, Brigitte Ruehle
  • Publication number: 20170338169
    Abstract: In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.
    Type: Application
    Filed: May 22, 2017
    Publication date: November 23, 2017
    Inventors: Joachim Mahler, Michael Bauer, Jochen Dangelmaier, Reimund Engl, Johann Gatterbauer, Frank Hille, Michael Huettinger, Werner Kanert, Heinrich Koerner, Brigitte Ruehle, Francisco Javier Santos Rodriguez, Antonio Vellei
  • Patent number: 9543199
    Abstract: An explanation is given of, inter alia, methods in which the barrier material is removed at a via bottom or at a via top area by long-term heat treatment. Concurrently or alternatively, interconnects are coated with barrier material in a simple and uncomplicated manner by means of the long-term heat treatment.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: January 10, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Oliver Aubel, Wolfgang Hasse, Martina Hommel, Heinrich Koerner
  • Patent number: 9390973
    Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: July 12, 2016
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Jens Pohl, Gottfried Beer, Heinrich Koerner
  • Patent number: 9312172
    Abstract: One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: April 12, 2016
    Assignee: Infineon Technologies AG
    Inventors: Dirk Meinhold, Heinrich Koerner, Wolfgang Dickenscheid
  • Patent number: 9269669
    Abstract: A multifunctional dielectric layer can be formed on a substrate, especially on an exposed metallic strip conductor system on a substrate. An additional metal layer is formed across the surface of the exposed metal strip conductors. The metal layer is then at least partially converted to a nonconducting metal oxide, the dielectric layer.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: February 23, 2016
    Assignee: Infineon Technologies AG
    Inventors: Johann Helneder, Markus Schwerd, Thomas Goebel, Andrea Mitchell, Heinrich Koerner, Martina Hommel
  • Publication number: 20160049329
    Abstract: An explanation is given of, inter alia, methods in which the barrier material is removed at a via bottom or at a via top area by long-term heat treatment. Concurrently or alternatively, interconnects are coated with barrier material in a simple and uncomplicated manner by means of the long-term heat treatment.
    Type: Application
    Filed: December 23, 2013
    Publication date: February 18, 2016
    Inventors: Oliver Aubel, Wolfgang Hasse, Martina Hommel, Heinrich Koerner
  • Patent number: 9263328
    Abstract: One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: February 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Dirk Meinhold, Heinrich Koerner, Wolfgang Dickenscheid
  • Publication number: 20150206797
    Abstract: One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.
    Type: Application
    Filed: March 30, 2015
    Publication date: July 23, 2015
    Inventors: Dirk Meinhold, Heinrich Koerner, Wolfgang Dickenscheid
  • Patent number: 8994179
    Abstract: One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: March 31, 2015
    Assignee: Infineon Technologies AG
    Inventors: Dirk Meinhold, Heinrich Koerner, Wolfgang Dickenscheid
  • Publication number: 20150054175
    Abstract: One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.
    Type: Application
    Filed: October 31, 2014
    Publication date: February 26, 2015
    Inventors: Dirk Meinhold, Heinrich Koerner, Wolfgang Dickenscheid
  • Patent number: 8946074
    Abstract: A method of forming a semiconductor device, comprising: providing a Si-containing layer; forming a barrier layer over said Si-containing layer, said barrier layer comprising a compound including a metallic element; forming a metallic nucleation_seed layer over said barrier layer, said nucleation_seed layer including said metallic element; and forming a metallic interconnect layer over said nucleation_seed layer, wherein said barrier layer and said nucleation_seed layer are formed without exposing said semiconductor device to the ambient atmosphere.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: February 3, 2015
    Assignee: Infineon Technologies AG
    Inventor: Heinrich Koerner