Abstract: Optical waveguide isolator (121) for monolithic integration with semiconductor light emitting diodes such as Fabry-Perot or ring laser diodes. The present optical isolator (121), with optical input port (95) and output pod (96), comprises a branching waveguide coupler (56). This branching waveguide coupler (56) has a waveguide stem (60) splitted at one end into two waveguide branches (57, 58) such that a light wave fed via said input pod (95) into a first of these branches (58), is guided via the waveguide stem (60) and the output pod (96) out of the device. A light wave fed to the isolator's output pod (96) is guided along the stem (60) and coupled into the second waveguide branch (57).

Abstract: A semiconductor laser diode comprises a waveguide formed by an active layer sandwiched in between upper and lower cladding layers, wherein the cladding layers comprise a material having a bandgap that differs from that of the active layer. The waveguide is deposited on a structured substrate having a surface pattern that causes the waveguide to be bent near its ends, i.e., near cleaved or etched facets of the completed laser device thereby providing a non-absorbing mirror (NAM) window structure. A laser beam, generated in the center, planar waveguide section, leaves the waveguide at the bend, continuing substantially unabsorbed and undeflected through the wider bandgap cladding layer material towards the mirror facet. An amphoteric dopant, used during growth of the layered waveguide structure, causes a reversal of the conductivity-type within the semiconductor material deposited above inclined surface regions.

Abstract: Automatic alignment of an optical waveguide to a ridge waveguide laser is accomplished by transferring the ridge structure of the laser to a substrate by etching a mirror groove. The transferred ridge structure serves as a base for the deposition of waveguide layers. The thickness of the waveguide layers are controlled during the deposition such that the waveguide core is laterally and vertically aligned to the lasing active layer of the laser structure.

Abstract: A GaAs/AlGaAs-transverse junction stripe (TJS) laser with p-n junction formation by crystal plane dependent doping is described. The laser structure includes a molecular beam epitaxy (MBE)-deposited hetero-structure comprising AlGaAs layers with an active GaAs layer sandwiched therebetween. These layers are grown on the patterned surface of a GaAs substrate which provides (100)-plane oriented planar ridges and grooves, the edges being (111A)-plane oriented. p-n homojunctions are formed in the GaAs layer at the intersections of the (111A) and (100) crystal planes. Ohmic contacts are provided for applying currents of at least the threshold level of the junctions. These TJS lasers can be used to form 1- or 2-dimensional arrays of phase-coupled lasers for providing high optical power output.

Abstract: A method for the fabrication of self-aligned MESFET structures with a recessed refractory submicron gate. After channel formation on a semi-insulating (SI) substrate, which may consist of a III-V compound semiconductor such as GaAs, with subsequent annealing, refractory gate material is deposited and patterned. This is followed by the overgrowth of a highly doped contact layer of, e.g., GaAs, using MOCVD of MBE processes resulting in poly-crystalline material over the gate "mask" and mono-crystalline material on exposed semiconductor surfaces. Next, the poly-crystalline material is removed in a selective etch process, this step being followed by the deposition of source and drain electrodes. In order to further improve process reliability, insulating sidewalls are provided at the vertical edges of the gate to avoid source-gate and drain-gate shorts.

Abstract: Planar junction Josephson interferometer in which the junctions (24) are "buried" underneath the interferometer bridge (27) connecting the junction counter-electrodes (25). The insulation (26) that separates the common base electrode (22) from the bridge (27) is extended between the bridge and the upper surfaces of the counter-electrodes. This design permits, without decreasing the interferometer loop inductance, a reduction of the interferometer area and thus results in a higher packaging density in logic or memory applications.The buried junction concept can be applied in symmetric or asymmetric interferometer designs with virtually any number of junctions, any type of input current control or current feeding scheme.The interferometer can be produced using conventional evaporation, photo-resist, and etch processes based on optical lithography. Further area reduction is achieved in applying e-beam or x-ray technology.