Abstract: In order to develop a circuit arrangement and also a method for calibrating at least one activation signal provided for a voltage-controlled oscillator such that the expenditure of energy is as low as possible and the output frequency is as high as possible, it is proposed—that the respective number of clock cycles for at least one calibration oscillator and at least one reference oscillator associated with the calibration oscillator is counted by means of at least one clock cycle counter connected downstream of the calibration oscillator and the reference oscillator and a clock error resulting from the difference between these two numbers of clock cycles is integrated and—that the clock error is converted by means of at least one digital-to-analog converter connected downstream of the clock counter into analog tuning signals from which the calibrated activation signal is derived.

Abstract: In order to provide a circuit arrangement (100) and also a method for clock and/or data recovery (CDR) having low power consumption, having low power loss and also having scalability of the power loss from the clock and/or data recovery at the data rate, at least one frequency regulation circuit and at least one phase regulation circuit are proposed, wherein firstly only the frequency regulation circuit is active for the purpose of setting the frequency on the basis of the data rate that can be applied to the data input and then changeover to the phase regulation circuit occurs for the purpose of ascertaining the phase difference between the data input and the clock input.

Abstract: In order to develop a circuit arrangement (100) and also a method for calibrating at least one activation signal (Vbb) provided for a voltage-controlled oscillator (10) such that the expenditure of energy is as low as possible and the output frequency is as high as possible, it is proposed—that the respective number of clock cycles (N) for at least one calibration oscillator (50) and at least one reference oscillator (30) associated with the calibration oscillator (50) is counted by means of at least one clock cycle counter (70) connected downstream of the calibration oscillator (50) and the reference oscillator (30) and a clock error (DE) resulting from the difference between these two numbers of clock cycles (N) is integrated and—that the clock error (DE) is converted by means of at least one digital-to-analogue converter (90) connected downstream of the clock counter (70) into analogue tuning signals (Vcm, Vcm?, Vcm+) from which the calibrated activation signal (Vbb) is derived.

Abstract: In order to provide a circuit arrangement (100) and also a method for clock and/or data recovery (CDR) having low power consumption, having low power loss and also having scalability of the power loss from the clock and/or data recovery at the data rate, at least one frequency regulation circuit and at least one phase regulation circuit are proposed, wherein firstly only the frequency regulation circuit is active for the purpose of setting the frequency on the basis of the data rate that can be applied to the data input and then changeover to the phase regulation circuit occurs for the purpose of ascertaining the phase difference between the data input and the clock input.

Abstract: A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.

Abstract: A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.

Abstract: A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.

Abstract: A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.

Abstract: The invention relates to a phase locked loop or “PLL” (12) and a method for the operation of a PLL (12), wherein a controllable oscillator (DCO) generates an output signal (CKout) and can be switched over between a first clock signal (CKin1 or CKin2) and a second clock signal (CKin2 or CKin1) for use as the input clock signal of the PLL (12). According to the invention, for the clock signal (CKin1 or CKin2) currently being used to generate the output signal (CKout), a phase difference between this clock signal and the output signal (CKout) is determined and used for the control of the oscillator (DCO), whereas for the clock signal (CKin2 or CKin1) currently not being used to generate the output signal (CKout), its frequency difference with respect to the output signal (CKout) is determined and stored and continuously updated and provided for the control of the oscillator (DCO) after the switch-over to this clock signal previously not being used.

Abstract: The present invention concerns a digital phase detector (PD) and also a method for digital phase detection, as can in particular be used e.g. in a so-called phase locked loop (PLL). According to the invention a digital phase detection signal (PD_OUT) is obtained, which specifies the phasing of an input clock signal (PD_IN) with reference to a higher frequency sampling clock signal (CK). In order hereby to overcome the limitation of the phase resolution as a result of a limited performance capability, in particular limited speed of the electronic components of a sampling device (14), a new kind of concept is used, in which the sampling clock signal (CK) is not immediately used for sampling (14), but is subjected beforehand to a digitally adjustable phase displacement (12). There originates an “auxiliary sampling clock signal” (CK<1:8>). The sampling (14) delivers a first, more significant digital component (OUT1<9:0>) of the phase detection signal (PD_OUT).

Abstract: The present invention concerns a digital phase detector (PD) and also a method for digital phase detection, as can in particular be used e.g. in a so-called phase locked loop (PLL). According to the invention a digital phase detection signal (PD_OUT) is obtained, which specifies the phasing of an input clock signal (PD_IN) with reference to a higher frequency sampling clock signal (CK). In order hereby to overcome the limitation of the phase resolution as a result of a limited performance capability, in particular limited speed of the electronic components of a sampling device (14), a new kind of concept is used, in which the sampling clock signal (CK) is not immediately used for sampling (14), but is subjected beforehand to a digitally adjustable phase displacement (12). There originates an “auxiliary sampling clock signal” (CK<1:8>). The sampling (14) delivers a first, more significant digital component (OUT1<9:0>) of the phase detection signal (PD_OUT).

Abstract: The invention relates to a phase locked loop or “PLL” (12) and a method of operating a PLL (12), wherein a controllable oscillator (DCO) generates an output signal (CKout) and it is possible to switch between a first clock (CKin1 or CKin2) and a second clock (CKin2 or CKin1) for use as a PLL (12) input clock. In accordance with the invention, for the clock (CKin1 or CKin2) currently being used to generate the output signal (CKout) a phase difference is determined between this clock and a preset phase-shifted version (CK<1:8>) of the output signal (CKout) and is used to control the oscillator (DCO), whereas for the clock (CKin2 or CKin1) not currently being used to generate the output signal (CKout), the phase shift is adjusted.

Abstract: The invention concerns a phase locked loop or “PLL” (12) as well as a method for the operation of a PLL, in which a controllable oscillator (DCO) generates an output signal (CKout) of the phase locked loop, and a phase detector (PD) determines a phase difference between a clock signal (CKin) used as an input clock signal of the PLL (12), and the PLL output signal (CKout), and provides a phase detector output signal (PD_OUT) synchronising the oscillator (DCO) with the clock signal (CKin) used.

Abstract: The invention relates to a phase locked loop or “PLL” (12) and a method for the operation of a PLL (12), wherein a controllable oscillator (DCO) generates an output signal (CKout) and can be switched over between a first clock signal (CKin1 or CKin2) and a second clock signal (CKin2 or CKin1) for use as the input clock signal of the PLL (12). According to the invention, for the clock signal (CKin1 or CKin2) currently being used to generate the output signal (CKout), a phase difference between this clock signal and the output signal (CKout) is determined and used for the control of the oscillator (DCO), whereas for the clock signal (CKin2 or CKin1) currently not being used to generate the output signal (CKout), its frequency difference with respect to the output signal (CKout) is determined and stored and continuously updated and provided for the control of the oscillator (DCO) after the switch-over to this clock signal previously not being used.

Abstract: A digital phase detector compares the output clock signal of the oscillator with the reference clock signal, an analog phase detector, and a lock detection circuit connected to a digital phase detector and an analog phase detector for avoiding a phase quantization error. The lock detection circuit activates the analog phase detector to run simultaneously with a digital phase detector if the phase error is zero. The activated analog phase detector regulates the output clock signal of the digitally controllable oscillator in a continuously variable manner until the respective clock signal edges of the output clock signal and the reference clock signal are fully synchronous. The lock detection circuit deactivates the analog phase detector and continuously checks and regulates the digital phase detector until the phase error between the output clock signal and the reference clock signal is zero.

Abstract: The output driver circuit of an integrated circuit has several pairs of driver circuits and driver control circuits as well as a control device. Each pair of driver control circuit and driver circuit forms a driver stage. The driver stages are connected in series. Based on the input signal of the output driver circuit, the control device switches the signal direction through the succession of driver stages in such a way that, at the time the output driver circuit is switched either on or off, the driver stages are switched in a time delayed manner, whereby current pulses on the feeding lines and disturbance voltages induced in inductive loads are reduced.

Abstract: The output driver circuit of an integrated circuit has several pairs of driver circuits and driver control circuits as well as a control device. Each pair of driver control circuit and driver circuit forms a driver stage. The driver stages are connected in series. Based on the input signal of the output driver circuit, the control device switches the signal direction through the succession of driver stages in such a way that, at the time the output driver circuit is switched either on or off, the driver stages are switched in a time delayed manner, whereby current pulses on the feeding lines and disturbance voltages induced in inductive loads are reduced.

Abstract: A phase-locked loop includes a switched phase detector, a loop filter and an oscillator connected in series, as well as a device for technology compensation, in particular a course control device. An operating point is adjusted during a starting phase of the phase-locked loop through the use of the course control device in such a way that the damping and natural frequency of the phase-locked loop is independent of fluctuations in technology parameters.

Abstract: A phase-locked loop configuration includes a controllable delay device having a signal path with at least one inverter having supply lines, at least one field effect transistor having a load path, and at least one capacitor connecting the load path transversely to the signal path. A phase detector receives a reference signal and receives an input signal through the delay device. A first controller is connected downstream of the phase detector for controlling the load path of the at least one field effect transistor in the delay device. At least one pair of further field-effect transistors has load paths connected into the supply lines of the at least one inverter. A second controller is connected downstream of the phase detector for controlling the load paths of the further field effect transistors.

Abstract: A circuit configuration includes a controllable oscillator issuing an output signal. A phase detector is acted upon by a reference signal and by the output signal of the oscillator. A first charge pump is controllable by the phase detector and has an input connected to the phase detector and an output. A loop filter is connected between the first charge pump and the oscillator for triggering the oscillator. A second charge pump is connected parallel to the output of the first charge pump.