Patents by Inventor Helmut Reinig
Helmut Reinig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11171856Abstract: An apparatus is provided which comprises: a first network interface (NI) to receive data from a source; a second NI coupled to a target; and a circuitry to generate a sequence of source timestamps and a sequence of target timestamps, wherein the first NI is to receive the sequence of source timestamps, and associate a first source timestamp of the sequence of source timestamps with the data, and wherein the second NI is to receive: the data with the first source timestamp from the first NI and the sequence of target timestamps from the circuitry, the second NI to generate a timestamp for the data, based at least in part on the first source timestamp and a first target timestamp of the sequence of target timestamps.Type: GrantFiled: December 7, 2017Date of Patent: November 9, 2021Assignee: INTEL CORPORATIONInventors: Pradeep Kumar, Amit Badole, Arumugam Vijayaraman, Helmut Reinig, Patrik Eder, Vladimir Todorov, Abhiram Anantharamu
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Patent number: 11140023Abstract: An apparatus is provided which comprises: a plurality of data routers to route data packets, wherein the plurality of data routers comprises: a first data router comprising a trace port, and a second data router coupled to a component; and one or more trace routers to route trace information of the apparatus, wherein a first trace router of the one or more trace routers is coupled to the trace port, and wherein the first trace router is to route configuration information from the component to the trace port, the configuration information to configure the trace port.Type: GrantFiled: September 19, 2017Date of Patent: October 5, 2021Assignee: INTEL CORPORATIONInventors: Simona Bernardi, Helmut Reinig, Todor M. Mladenov
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Patent number: 10868622Abstract: Embodiments of the present disclosure may relate to an apparatus with a first component and a second component coupled with the first component by a plurality of signal wires. A first wire of the plurality of signal wires may be to carry a command byte of a packet and a first data byte of the packet from the first component to the second component. A second wire of the plurality of signal wires may be to carry a second data byte of the packet from the first component to the second component when the first signal wire carries the command byte of the packet and carry a third data byte of the packet from the first component to the second component when the first signal wire carries the first data byte of the packet. Other embodiments may be described or claimed.Type: GrantFiled: June 22, 2017Date of Patent: December 15, 2020Assignee: Intel IP CorporationInventors: Todor M. Mladenov, Helmut Reinig, Simona Bernardi
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Publication number: 20190089582Abstract: An apparatus is provided which comprises: a plurality of data routers to route data packets, wherein the plurality of data routers comprises: a first data router comprising a trace port, and a second data router coupled to a component; and one or more trace routers to route trace information of the apparatus, wherein a first trace router of the one or more trace routers is coupled to the trace port, and wherein the first trace router is to route configuration information from the component to the trace port, the configuration information to configure the trace port.Type: ApplicationFiled: September 19, 2017Publication date: March 21, 2019Applicant: Intel CorporationInventors: Simona Bernardi, Helmut Reinig, Todor M. Mladenov
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Publication number: 20190036803Abstract: An apparatus is provided which comprises: a first network interface (NI) to receive data from a source; a second NI coupled to a target; and a circuitry to generate a sequence of source timestamps and a sequence of target timestamps, wherein the first NI is to receive the sequence of source timestamps, and associate a first source timestamp of the sequence of source timestamps with the data, and wherein the second NI is to receive: the data with the first source timestamp from the first NI and the sequence of target timestamps from the circuitry, the second NI to generate a timestamp for the data, based at least in part on the first source timestamp and a first target timestamp of the sequence of target timestamps.Type: ApplicationFiled: December 7, 2017Publication date: January 31, 2019Applicant: Intel IP CorporationInventors: Pradeep Kumar, Amit Badole, Arumugam Vijayaraman, Helmut Reinig, Patrik Eder, Vladimir Todorov, Abhiram Anantharamu
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Publication number: 20180375602Abstract: Embodiments of the present disclosure may relate to an apparatus with a first component and a second component coupled with the first component by a plurality of signal wires. A first wire of the plurality of signal wires may be to carry a command byte of a packet and a first data byte of the packet from the first component to the second component. A second wire of the plurality of signal wires may be to carry a second data byte of the packet from the first component to the second component when the first signal wire carries the command byte of the packet and carry a third data byte of the packet from the first component to the second component when the first signal wire carries the first data byte of the packet. Other embodiments may be described or claimed.Type: ApplicationFiled: June 22, 2017Publication date: December 27, 2018Inventors: Todor M. Mladenov, Helmut Reinig, Simona Bernardi
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Patent number: 10127171Abstract: A circuit arrangement, network-on-chip, and a method for transmitting information are disclosed. In one embodiment, an electrical circuit is provided comprising a plurality of circuit blocks comprising a first circuit block, a second circuit block, and a third circuit block, and a connection structure coupled to the plurality of circuit blocks, wherein the first circuit block is configured to send a request comprising information corresponding to the request and an address onto the connection structure, wherein the second circuit block is configured to initiate a transmission onto the connection structure in response to receiving the request, and wherein the third circuit block is configured to receive the transmission and wherein the address is assigned to the third circuit block.Type: GrantFiled: September 2, 2010Date of Patent: November 13, 2018Assignee: Infineon Technologies AGInventors: Helmut Reinig, Soeren Sonntag
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Publication number: 20180165240Abstract: A network interface is provided which comprises: a first buffer configured to buffer a first flow of a first type of commands from a first device to a second device, wherein the first device is configured in accordance with a first bus interconnect protocol and the second device is configured in accordance with a second bus interconnect protocol; a second buffer configured to buffer a second flow of a second type of commands from the first device to the second device; and an arbiter configured to arbitrate between the first flow and the second flow, and selectively output one or more commands of the first type and one or more commands of the second type.Type: ApplicationFiled: December 8, 2016Publication date: June 14, 2018Inventors: Helmut Reinig, Todor M. Mladenov, Simona Bernardi, Robert De Gruijl
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Publication number: 20160173398Abstract: In one embodiment, an apparatus comprises: a source agent including at least one logic unit to perform instructions; an encoder to encode a burst command portion of a packet having a first field to indicate a burst size and a second field to indicate a data width of one of the source agent and a destination agent, where the burst size and the data width are to remain fixed when the packet is to be re-sized one or more times during transmission from the source agent to the destination agent; and transmission logic to transmit the packet including the burst command portion. Other embodiments are described and claimed.Type: ApplicationFiled: December 12, 2014Publication date: June 16, 2016Inventor: Helmut Reinig
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Patent number: 9262356Abstract: An arbiter device arbitrating resource requests received at a plurality of input ports is proposed, which comprises an arbiter circuit that selects an input port to which a resource request is to be granted and successively grants a number of resource requests received at the selected input port.Type: GrantFiled: December 15, 2006Date of Patent: February 16, 2016Assignee: Lantiq Beteiligungs-GmbH & Co.KGInventors: Soren Sonntag, Helmut Reinig
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Publication number: 20150277949Abstract: A processing system includes an interconnect and a processing core, coupled to the interconnect, to execute a plurality of virtual machines each being identified by a respective identifier, and tag, by an identifier of the first virtual machine, a first transaction initiated by a first virtual machine to access the interconnect.Type: ApplicationFiled: March 27, 2014Publication date: October 1, 2015Inventors: THIAM WAH LOH, GAUTHAM N. CHINYA, STEPHEN J. ROBINSON, REZA FORTAS, HONG WANG, HELMUT REINIG, PER HAMMARLUND, DEEPAK A. MATHAIKUTTY, CHRISTIAN ERBEN
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Patent number: 9037688Abstract: A system includes a functional unit having a plurality of components. The system further includes trace resources for tracking processes executed by the functional unit. The trace resources include a network configuration having a plurality of nodes and a plurality of monitors, wherein each of the monitors is coupled to a node and is configured to determine trace information of a component. Further, a trace unit is coupled to the network configuration.Type: GrantFiled: December 27, 2011Date of Patent: May 19, 2015Assignee: Intel Mobile Communications GmbHInventors: Vladimir Todorov, Helmut Reinig, Alberto Ghiribaldi, Patrik Eder
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Patent number: 8832664Abstract: Apparatuses and methods relate to tracing exchanges of a plurality of signals, including requests and responses, made between a master device and a slave device of the system on chip. The apparatuses and methods further relate to tracking the number of requests and the number of responses made before and after tracing is activated for determining which responses to trace after tracing is activated and for determining which remaining number of responses to trace after tracing is deactivated.Type: GrantFiled: July 20, 2012Date of Patent: September 9, 2014Assignee: Intel Mobile Communications GmbHInventors: Andre Oliver Richter, Helmut Reinig, Vladimir Todorov
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Publication number: 20140026126Abstract: A trace monitor configured to trace an exchange of a plurality of signals between a master device and a slave device of the system on chip, wherein the plurality of signals have a number of requests and a number of responses; and track the number of requests and the number of responses made before and after tracing is activated to determine which Reponses of the number of responses to trace after tracing is activated and a remaining number of responses to trace after tracing is deactivated.Type: ApplicationFiled: July 20, 2012Publication date: January 23, 2014Applicant: INTEL MOBILE COMMUNICATIONS GMBHInventors: Andre Oliver Richter, Helmut Reinig, Vladimir Todorov
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Publication number: 20130166701Abstract: A system includes a functional unit having a plurality of components. The system further includes trace resources for tracking processes executed by the functional unit. The trace resources include a network configuration having a plurality of nodes and a plurality of monitors, wherein each of the monitors is coupled to a node and is configured to determine trace information of a component. Further, a trace unit is coupled to the network configuration.Type: ApplicationFiled: December 27, 2011Publication date: June 27, 2013Applicant: Intel Mobile Communications GmbHInventors: Vladimir Todorov, Helmut Reinig, Alberto Ghiribaldi, Patrik Eder
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Patent number: 8352695Abstract: A memory system includes a selection element for selecting a selectable access rate from a plurality of access rates and a memory element for providing or for accepting data at the selectable access rate.Type: GrantFiled: May 29, 2007Date of Patent: January 8, 2013Assignee: Lantiq Deutschland GmbHInventors: Christian Klein, Stefan Linz, Helmut Reinig
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Publication number: 20110075656Abstract: A circuit arrangement, network-on-chip, and a method for transmitting information are disclosed. In one embodiment, an electrical circuit is provided comprising a plurality of circuit blocks comprising a first circuit block, a second circuit block, and a third circuit block, and a connection structure coupled to the plurality of circuit blocks, wherein the first circuit block is configured to send a request comprising information corresponding to the request and an address onto the connection structure, wherein the second circuit block is configured to initiate a transmission onto the connection structure in response to receiving the request, and wherein the third circuit block is configured to receive the transmission and wherein the address is assigned to the third circuit block.Type: ApplicationFiled: September 2, 2010Publication date: March 31, 2011Inventors: Helmut REINIG, Soeren SONNTAG
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Patent number: 7734856Abstract: Embodiments related to arbitration are described and depicted.Type: GrantFiled: August 22, 2007Date of Patent: June 8, 2010Assignee: Lantiq Deutschland GmbHInventors: Helmut Reinig, Soeren Sonntag
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Publication number: 20090055566Abstract: Embodiments related to arbitration are described and depicted.Type: ApplicationFiled: August 22, 2007Publication date: February 26, 2009Applicant: INFINEON TECHNOLOGIES AGInventors: Helmut REINIG, Soeren SONNTAG
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Publication number: 20080147944Abstract: An arbiter device arbitrating resource requests received at a plurality of input ports is proposed, which comprises an arbiter circuit that selects an input port to which a resource request is to be granted and successively grants a number of resource requests received at the selected input port.Type: ApplicationFiled: December 15, 2006Publication date: June 19, 2008Applicant: Infineon Technologies AGInventors: Soren Sonntag, Helmut Reinig