Patents by Inventor Helmut Reinig

Helmut Reinig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10868622
    Abstract: Embodiments of the present disclosure may relate to an apparatus with a first component and a second component coupled with the first component by a plurality of signal wires. A first wire of the plurality of signal wires may be to carry a command byte of a packet and a first data byte of the packet from the first component to the second component. A second wire of the plurality of signal wires may be to carry a second data byte of the packet from the first component to the second component when the first signal wire carries the command byte of the packet and carry a third data byte of the packet from the first component to the second component when the first signal wire carries the first data byte of the packet. Other embodiments may be described or claimed.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: December 15, 2020
    Assignee: Intel IP Corporation
    Inventors: Todor M. Mladenov, Helmut Reinig, Simona Bernardi
  • Publication number: 20190089582
    Abstract: An apparatus is provided which comprises: a plurality of data routers to route data packets, wherein the plurality of data routers comprises: a first data router comprising a trace port, and a second data router coupled to a component; and one or more trace routers to route trace information of the apparatus, wherein a first trace router of the one or more trace routers is coupled to the trace port, and wherein the first trace router is to route configuration information from the component to the trace port, the configuration information to configure the trace port.
    Type: Application
    Filed: September 19, 2017
    Publication date: March 21, 2019
    Applicant: Intel Corporation
    Inventors: Simona Bernardi, Helmut Reinig, Todor M. Mladenov
  • Publication number: 20190036803
    Abstract: An apparatus is provided which comprises: a first network interface (NI) to receive data from a source; a second NI coupled to a target; and a circuitry to generate a sequence of source timestamps and a sequence of target timestamps, wherein the first NI is to receive the sequence of source timestamps, and associate a first source timestamp of the sequence of source timestamps with the data, and wherein the second NI is to receive: the data with the first source timestamp from the first NI and the sequence of target timestamps from the circuitry, the second NI to generate a timestamp for the data, based at least in part on the first source timestamp and a first target timestamp of the sequence of target timestamps.
    Type: Application
    Filed: December 7, 2017
    Publication date: January 31, 2019
    Applicant: Intel IP Corporation
    Inventors: Pradeep Kumar, Amit Badole, Arumugam Vijayaraman, Helmut Reinig, Patrik Eder, Vladimir Todorov, Abhiram Anantharamu
  • Publication number: 20180375602
    Abstract: Embodiments of the present disclosure may relate to an apparatus with a first component and a second component coupled with the first component by a plurality of signal wires. A first wire of the plurality of signal wires may be to carry a command byte of a packet and a first data byte of the packet from the first component to the second component. A second wire of the plurality of signal wires may be to carry a second data byte of the packet from the first component to the second component when the first signal wire carries the command byte of the packet and carry a third data byte of the packet from the first component to the second component when the first signal wire carries the first data byte of the packet. Other embodiments may be described or claimed.
    Type: Application
    Filed: June 22, 2017
    Publication date: December 27, 2018
    Inventors: Todor M. Mladenov, Helmut Reinig, Simona Bernardi
  • Patent number: 10127171
    Abstract: A circuit arrangement, network-on-chip, and a method for transmitting information are disclosed. In one embodiment, an electrical circuit is provided comprising a plurality of circuit blocks comprising a first circuit block, a second circuit block, and a third circuit block, and a connection structure coupled to the plurality of circuit blocks, wherein the first circuit block is configured to send a request comprising information corresponding to the request and an address onto the connection structure, wherein the second circuit block is configured to initiate a transmission onto the connection structure in response to receiving the request, and wherein the third circuit block is configured to receive the transmission and wherein the address is assigned to the third circuit block.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: November 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Helmut Reinig, Soeren Sonntag
  • Publication number: 20180165240
    Abstract: A network interface is provided which comprises: a first buffer configured to buffer a first flow of a first type of commands from a first device to a second device, wherein the first device is configured in accordance with a first bus interconnect protocol and the second device is configured in accordance with a second bus interconnect protocol; a second buffer configured to buffer a second flow of a second type of commands from the first device to the second device; and an arbiter configured to arbitrate between the first flow and the second flow, and selectively output one or more commands of the first type and one or more commands of the second type.
    Type: Application
    Filed: December 8, 2016
    Publication date: June 14, 2018
    Inventors: Helmut Reinig, Todor M. Mladenov, Simona Bernardi, Robert De Gruijl
  • Publication number: 20160173398
    Abstract: In one embodiment, an apparatus comprises: a source agent including at least one logic unit to perform instructions; an encoder to encode a burst command portion of a packet having a first field to indicate a burst size and a second field to indicate a data width of one of the source agent and a destination agent, where the burst size and the data width are to remain fixed when the packet is to be re-sized one or more times during transmission from the source agent to the destination agent; and transmission logic to transmit the packet including the burst command portion. Other embodiments are described and claimed.
    Type: Application
    Filed: December 12, 2014
    Publication date: June 16, 2016
    Inventor: Helmut Reinig
  • Patent number: 9262356
    Abstract: An arbiter device arbitrating resource requests received at a plurality of input ports is proposed, which comprises an arbiter circuit that selects an input port to which a resource request is to be granted and successively grants a number of resource requests received at the selected input port.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: February 16, 2016
    Assignee: Lantiq Beteiligungs-GmbH & Co.KG
    Inventors: Soren Sonntag, Helmut Reinig
  • Publication number: 20150277949
    Abstract: A processing system includes an interconnect and a processing core, coupled to the interconnect, to execute a plurality of virtual machines each being identified by a respective identifier, and tag, by an identifier of the first virtual machine, a first transaction initiated by a first virtual machine to access the interconnect.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Inventors: THIAM WAH LOH, GAUTHAM N. CHINYA, STEPHEN J. ROBINSON, REZA FORTAS, HONG WANG, HELMUT REINIG, PER HAMMARLUND, DEEPAK A. MATHAIKUTTY, CHRISTIAN ERBEN
  • Patent number: 9037688
    Abstract: A system includes a functional unit having a plurality of components. The system further includes trace resources for tracking processes executed by the functional unit. The trace resources include a network configuration having a plurality of nodes and a plurality of monitors, wherein each of the monitors is coupled to a node and is configured to determine trace information of a component. Further, a trace unit is coupled to the network configuration.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: May 19, 2015
    Assignee: Intel Mobile Communications GmbH
    Inventors: Vladimir Todorov, Helmut Reinig, Alberto Ghiribaldi, Patrik Eder
  • Patent number: 8832664
    Abstract: Apparatuses and methods relate to tracing exchanges of a plurality of signals, including requests and responses, made between a master device and a slave device of the system on chip. The apparatuses and methods further relate to tracking the number of requests and the number of responses made before and after tracing is activated for determining which responses to trace after tracing is activated and for determining which remaining number of responses to trace after tracing is deactivated.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: September 9, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Andre Oliver Richter, Helmut Reinig, Vladimir Todorov
  • Publication number: 20140026126
    Abstract: A trace monitor configured to trace an exchange of a plurality of signals between a master device and a slave device of the system on chip, wherein the plurality of signals have a number of requests and a number of responses; and track the number of requests and the number of responses made before and after tracing is activated to determine which Reponses of the number of responses to trace after tracing is activated and a remaining number of responses to trace after tracing is deactivated.
    Type: Application
    Filed: July 20, 2012
    Publication date: January 23, 2014
    Applicant: INTEL MOBILE COMMUNICATIONS GMBH
    Inventors: Andre Oliver Richter, Helmut Reinig, Vladimir Todorov
  • Publication number: 20130166701
    Abstract: A system includes a functional unit having a plurality of components. The system further includes trace resources for tracking processes executed by the functional unit. The trace resources include a network configuration having a plurality of nodes and a plurality of monitors, wherein each of the monitors is coupled to a node and is configured to determine trace information of a component. Further, a trace unit is coupled to the network configuration.
    Type: Application
    Filed: December 27, 2011
    Publication date: June 27, 2013
    Applicant: Intel Mobile Communications GmbH
    Inventors: Vladimir Todorov, Helmut Reinig, Alberto Ghiribaldi, Patrik Eder
  • Patent number: 8352695
    Abstract: A memory system includes a selection element for selecting a selectable access rate from a plurality of access rates and a memory element for providing or for accepting data at the selectable access rate.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: January 8, 2013
    Assignee: Lantiq Deutschland GmbH
    Inventors: Christian Klein, Stefan Linz, Helmut Reinig
  • Publication number: 20110075656
    Abstract: A circuit arrangement, network-on-chip, and a method for transmitting information are disclosed. In one embodiment, an electrical circuit is provided comprising a plurality of circuit blocks comprising a first circuit block, a second circuit block, and a third circuit block, and a connection structure coupled to the plurality of circuit blocks, wherein the first circuit block is configured to send a request comprising information corresponding to the request and an address onto the connection structure, wherein the second circuit block is configured to initiate a transmission onto the connection structure in response to receiving the request, and wherein the third circuit block is configured to receive the transmission and wherein the address is assigned to the third circuit block.
    Type: Application
    Filed: September 2, 2010
    Publication date: March 31, 2011
    Inventors: Helmut REINIG, Soeren SONNTAG
  • Patent number: 7734856
    Abstract: Embodiments related to arbitration are described and depicted.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: June 8, 2010
    Assignee: Lantiq Deutschland GmbH
    Inventors: Helmut Reinig, Soeren Sonntag
  • Publication number: 20090055566
    Abstract: Embodiments related to arbitration are described and depicted.
    Type: Application
    Filed: August 22, 2007
    Publication date: February 26, 2009
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Helmut REINIG, Soeren SONNTAG
  • Publication number: 20080147944
    Abstract: An arbiter device arbitrating resource requests received at a plurality of input ports is proposed, which comprises an arbiter circuit that selects an input port to which a resource request is to be granted and successively grants a number of resource requests received at the selected input port.
    Type: Application
    Filed: December 15, 2006
    Publication date: June 19, 2008
    Applicant: Infineon Technologies AG
    Inventors: Soren Sonntag, Helmut Reinig
  • Publication number: 20070283077
    Abstract: A memory system includes a selection element for selecting a selectable access rate from a plurality of access rates and a memory element for providing or for accepting data at the selectable access rate.
    Type: Application
    Filed: May 29, 2007
    Publication date: December 6, 2007
    Inventors: Christian Klein, Stefan Linz, Helmut Reinig