Patents by Inventor Hem Takiar

Hem Takiar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stacked wire bonded semiconductor package with low profile bond line
    Patent number: 8432043
    Abstract: A low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with a plurality of redistribution pads formed over and electrically coupled to a plurality of bond pads. After the semiconductor die are formed and diced from the wafer, the die may be mounted to the substrate using a low profile reverse wire bond according to the present invention. In particular, a wedge bond may be formed between the wire and the redistribution pad without having to use a second wire bond ball on the die bond pad as in conventional reverse ball bonding processes.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: April 30, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Hem Takiar, Shrikar Bhagath
  • RADIATION-SHIELDED SEMICONDUCTOR DEVICE
    Publication number: 20130087895
    Abstract: A semiconductor device is disclosed including an electromagnetic radiation shield. The device may include a substrate having a shield ring defined in a conductance pattern on a surface of the substrate. One or more semiconductor die may be affixed and electrically coupled to the substrate. The one or more semiconductor die may then be encapsulated in molding compound. Thereafter, a metal may be plated around the molding compound and onto the shield ring to form an EMI/RFI shield for the device.
    Type: Application
    Filed: October 5, 2011
    Publication date: April 11, 2013
    Inventors: Suresh Kumar Upadhyayula, Hem Takiar, Chih-Chin Liao
  • Two-sided die in a four-sided leadframe based package
    Patent number: 8395246
    Abstract: A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: March 12, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Cheemen Yu, Vani Verma, Hem Takiar
  • Semiconductor package including flip chip controller at bottom of die stack
    Patent number: 8373268
    Abstract: A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: February 12, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Suresh Upadhyayula, Hem Takiar
  • Method of fabricating a two-sided die in a four-sided leadframe based package
    Patent number: 8349655
    Abstract: A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: January 8, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Cheeman Yu, Vani Verma, Hem Takiar
  • DISCRETE COMPONENT BACKWARD TRACEABILITY AND SEMICONDUCTOR DEVICE FORWARD TRACEABILITY
    Publication number: 20130006564
    Abstract: A system is disclosed for providing backward and forward traceability by a methodology which identifies discrete components (die, substrate and/or passives) that are included in a semiconductor device. The present technology further includes a system for generating a unique identifier and marking a semiconductor device with the unique identifier enabling the semiconductor device, and the discrete components within that device, to be tracked and traced through each process and test in the production of the semiconductor device.
    Type: Application
    Filed: October 4, 2010
    Publication date: January 3, 2013
    Inventors: Didier Chavet, Cheeman Yu, Hem Takiar, Frank Lu, Chih-Chiang Tung, Jiaming Shi
  • Method of fabricating a memory card using SiP/SMT hybrid technology
    Patent number: 8318535
    Abstract: A portable memory card formed from a multi-die assembly, and methods of fabricating same, are disclosed. One such multi-die assembly includes an LGA SiP semiconductor package and a leadframe-based SMT package both affixed to a PCB. The multi-die assembly thus formed may be encased within a standard lid to form a completed portable memory card, such as a standard SD™ card. Test pads on the LGA SiP package, used for testing operation of the package after it is fabricated, may also be used for physically and electrically coupling the LGA SiP package to the PCB.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: November 27, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Ning Ye, Robert C. Miller, Cheemen Yu, Hem Takiar, Andre McKenzie
  • EPOXY COATING ON SUBSTRATE FOR DIE ATTACH
    Publication number: 20120279651
    Abstract: A system and method are disclosed for applying a die attach epoxy to substrates on a panel of substrates. The system includes a window clamp having one or more windows through which the epoxy may be applied onto the substrate panel. The size and shape of the one or more windows correspond to the size and shape of the area on the substrate to receive the die attach epoxy. Once the die attach epoxy is sprayed onto the substrate through the windows of the window clamp, the die may be affixed to the substrate and the epoxy cured in one or more curing steps. The system may further include a clean-up follower for cleaning epoxy off of the window clamp, and a window cleaning mechanism for cleaning epoxy off of the sidewalls of the windows of the window clamp.
    Type: Application
    Filed: May 5, 2011
    Publication date: November 8, 2012
    Inventors: Wei Gu, Zhong Lu, Shrikar Bhagath, Chin-Tien Chiu, Hem Takiar, XiangYang Liu
  • COL-BASED SEMICONDUCTOR PACKAGE INCLUDING ELECTRICAL CONNECTIONS THROUGH A SINGLE LAYER LEADFRAME
    Publication number: 20120280378
    Abstract: A semiconductor package is disclosed including a leadframe, memory die and controller die, one or more of which are customized to facilitate electrical connection of the memory and controller die bond pads to the contact pads of the host device via the leadframe. By customizing one or more of the leadframe, memory die and controller die, an interposer layer normally required to connect the die in the semiconductor package with a host device may be omitted.
    Type: Application
    Filed: May 6, 2011
    Publication date: November 8, 2012
    Inventors: Suresh Upadhyayula, Ming Hsun Lee, Hem Takiar
  • Printed Circuit Board With Coextensive Electrical Connectors And Contact Pad Areas
    Publication number: 20120273968
    Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.
    Type: Application
    Filed: July 9, 2012
    Publication date: November 1, 2012
    Inventors: Chih-Chin Liao, Han-Shiao Chen, Chin-Tien Chiu, Ken Jian Ming Wang, Cheemen Yu, Hem Takiar
  • Stacked semiconductor package with localized cavities for wire bonding
    Patent number: 8294251
    Abstract: A semiconductor die and a low profile semiconductor package formed therefrom are disclosed. The semiconductor package may include at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with localized cavities through a bottom surface of the semiconductor die, along a side edge of the semiconductor die. The one or more localized cavities in a side take up less than the entire side. Thus, the localized cavities allow low height stacking of semiconductor die while providing each die with a high degree of structural integrity to prevent cracking or breaking of the die edge during fabrication.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: October 23, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Hem Takiar, Shrikar Bhagath, Cheemen Yu, Chih-Chin Liao
  • Method of fabricating stacked wire bonded semiconductor package with low profile bond line
    Patent number: 8241953
    Abstract: A method of fabricating a low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with a plurality of redistribution pads formed over and electrically coupled to a plurality of bond pads. After the semiconductor die are formed and diced from the wafer, the die may be mounted to the substrate using a low profile reverse wire bond according to the present invention. In particular, a wedge bond may be formed between the wire and the redistribution pad without having to use a second wire bond ball on the die bond pad as in conventional reverse ball bonding processes.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: August 14, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Hem Takiar, Shrikar Bhagath
  • Methods of promoting adhesion between transfer molded IC packages and injection molded plastics for creating over-molded memory cards
    Patent number: 8232145
    Abstract: A flash memory card and methods of manufacturing same are disclosed. The card includes a semiconductor package fabricated to receive a single-sided or double-sided lid. A surface of the semiconductor package may be formed with holes, trenches and/or pockmarks. After the holes, trenches and/or pockmarks are formed, a lid may be attached to the package surface in an injection molding process. During the injection molding process, the molten plastic flows into the holes, trenches and/or pockmarks to interconnect with the surface of the semiconductor package. Thus, when the molten plastic hardens, the holes, trenches and/or pockmarks ensure that the lid remains firmly attached to semiconductor package.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: July 31, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Che-Jung Chang, Chin-Tien Chiu, Cheeman Yu, Hem Takiar, Jack Chang Chien, Ning Liu
  • Printed circuit board with coextensive electrical connectors and contact pad areas
    Patent number: 8217522
    Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: July 10, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Chih-Chin Liao, Han-Shiao Chen, Chin-Tien Chiu, Ken Jian Ming Wang, Cheeman Yu, Hem Takiar
  • Semiconductor die having a redistribution layer
    Patent number: 8212360
    Abstract: A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: July 3, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Chien-Ko Liao, Chin-Tien Chiu, Jack Chang Chien, Cheemen Yu, Hem Takiar
  • HIDDEN PLATING TRACES
    Publication number: 20120164828
    Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.
    Type: Application
    Filed: March 2, 2012
    Publication date: June 28, 2012
    Inventors: Hem Takiar, Cheeman Yu, Ken Jian Ming Wang, Chin-Tien Chiu, Han-Shiao Chen, Chih-Chin Liao
  • PRE-TREATMENT OF MEMORY CARDS FOR BINDING GLUE AND OTHER CURABLE FLUIDS
    Publication number: 20120146247
    Abstract: A memory device is disclosed including at least one surface pre-treated to roughen the surface for better adhesion of a curable fluid such as glue or ink on the surface. The surface of the memory device may be pre-treated by scoring lines in the surface with a laser or by forming discrete deformations with a particle blaster. The surface may also be roughened by providing a roughened pattern on a mold plate during an encapsulation process. In further examples, the surface may be chemically pre-treated to roughen the surface and/or increase the adhesion energy of the surface.
    Type: Application
    Filed: June 8, 2011
    Publication date: June 14, 2012
    Inventors: Itzhak Pomerantz, Shiv Kumar, Robert Miller, Chin-Tien Chiu, Peng Fu, Cheeman Yu, Hem Takiar, Chih Chiang Tung, Kaiyou Qian, Rahav Yairi
  • PRE-TREATMENT OF MEMORY CARDS FOR INK JET PRINTING
    Publication number: 20120081860
    Abstract: A memory device is disclosed including at least one surface pre-treated to roughen the surface for better adhesion of ink on the surface. The surface of the memory device may be pre-treated by scoring lines in the surface with a laser or by forming discrete deformations with a particle blaster. The surface may also be roughened by providing a roughened pattern on a mold plate during an encapsulation process. In further examples, the surface may be chemically pre-treated to roughen the surface and/or increase the adhesion energy of the surface.
    Type: Application
    Filed: October 4, 2010
    Publication date: April 5, 2012
    Inventors: Itzhak Pomerantz, Shiv Kumar, Robert Miller, Chin-Tien Chiu, Peng Fu, Cheeman Yu, Hem Takiar, Chih Chiang Tung, Kaiyou Qian
  • Hidden plating traces
    Patent number: 8129272
    Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: March 6, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Hem Takiar, Cheeman Yu, Ken Jian Ming Wang, Chin-Tien Chiu, Han-Shiao Chen, Chih-Chin Liao
  • Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages
    Patent number: 8110439
    Abstract: An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: February 7, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Cheeman Yu, Chi-Chin Liao, Hem Takiar