Abstract: In an embodiment, a pressure sensor module includes a base electrode surrounding at least a part of a bottom electrode, an anchor arrangement on top of the base electrode including at least two electrically conductive walls that both surround at least the part of the bottom electrode and an electrically conductive layer that covers at least the bottom electrode and the anchor arrangement such that a cavity is formed between the bottom electrode, the anchor arrangement and the electrically conductive layer, wherein, on at least one side of the cavity, a proportionate area of the electrically conductive walls in a cross section extending from a surface of an inner wall of the anchor arrangement facing the cavity to a surface of an outermost wall of the anchor arrangement facing away from the cavity in a plane parallel to a plane of the bottom electrode is equal to or less than 10%.

Abstract: A sensor package and a method for producing a sensor package are disclosed. In an embodiment a method for producing a sensor package includes providing a carrier including electric conductors, fastening a dummy die or interposer to the carrier, providing an ASIC device including an integrated sensor element and fastening the ASIC device to the dummy die or interposer.

Abstract: The sensor package comprises a carrier (1) including electric conductors (13), an ASIC device (6) and a sensor element (7), which is integrated in the ASIC device (6). A dummy die or interposer (4) is arranged between the carrier (1) and the ASIC device (6). The dummy die or interposer (4) is fastened to the carrier (1), and the ASIC device (6) is fastened to the dummy die or interposer (4).

Abstract: A pressure sensor module comprises a base electrode surrounding at least a part of a bottom electrode, and an anchor arrangement on top of the base electrode comprising at least two electrically conductive walls that both surround at least a part of the bottom electrode. The pressure sensor module further comprises an electrically conductive layer that covers at least the bottom electrode and the anchor arrangement such that a cavity is formed between the bottom electrode, the anchor arrangement and the electrically conductive layer. The proportionate area of the electrically conductive walls in a cross section extending from the surface of the inner wall of the anchor arrangement facing the cavity to the surface of the outermost wall of the anchor arrangement facing away from the cavity in a plane parallel to the plane of the bottom electrode is equal to or less than 10%.

Abstract: The sensor package comprises a carrier (1) including electric conductors (13), an ASIC device (6) and a sensor element (7), which is integrated in the ASIC device (6). A dummy die or interposer (4) is arranged between the carrier (1) and the ASIC device (6). The dummy die or interposer (4) is fastened to the carrier (1), and the ASIC device (6) is fastened to the dummy die or interposer (4).

Abstract: A sensor package comprises a sensor chip bonded to an intermediate carrier, with the sensor element over an opening in the carrier. The package is for soldering to a board, during which the intermediate carrier protects the sensor part of the sensor chip.

Abstract: One example discloses an chip, comprising: a substrate; a first side of a passivation layer coupled to the substrate; a device, having a device height and a cavity, wherein a first device surface is coupled to a second side of the passivation layer which is opposite to the first side of the passivation layer; and a set of structures coupled to the second side of the passivation layer and configured to have a structure height greater than or equal to the device height.

Abstract: One example discloses an chip, comprising: a substrate; a first side of a passivation layer coupled to the substrate; a device, having a device height and a cavity, wherein a first device surface is coupled to a second side of the passivation layer which is opposite to the first side of the passivation layer; and a set of structures coupled to the second side of the passivation layer and configured to have a structure height greater than or equal to the device height.

Abstract: One example embodiment discloses a chip having a chip area, wherein the chip area includes: an overhang area; a rigid coupling area, having a set of rigid coupling points, located on one side of the overhang area; and a flexible coupling area, having a set of flexible coupling points, located on a side of the overhang area opposite to the a rigid coupling area. Another example embodiment discloses a method for fabricating a die interconnect, comprising: fabricating a rigid coupler area, having a set of rigid coupler points, within a chip having a chip area; defining an overhang area within the chip area and abutted to the rigid coupler area; and fabricating a flexible coupler area, having a set of flexible coupler points, within the chip area abutted to a side of the overhang area opposite to the rigid coupler area.

Abstract: One example embodiment discloses a chip having a chip area, wherein the chip area includes: an overhang area; a rigid coupling area, having a set of rigid coupling points, located on one side of the overhang area; and a flexible coupling area, having a set of flexible coupling points, located on a side of the overhang area opposite to the a rigid coupling area. Another example embodiment discloses a method for fabricating a die interconnect, comprising: fabricating a rigid coupler area, having a set of rigid coupler points, within a chip having a chip area; defining an overhang area within the chip area and abutted to the rigid coupler area; and fabricating a flexible coupler area, having a set of flexible coupler points, within the chip area abutted to a side of the overhang area opposite to the rigid coupler area.

Abstract: An integrated circuit package for an integrated circuit having one or more sensor elements in a sensor element area of the circuit. An encapsulation covers bond wires but leaves an opening over the sensor element area. A protection layer is provided over the integrated circuit over which the encapsulation extends, and it has a channel around the sensor element area to act as a trap for any encapsulation material which has crept into the opening area.

Abstract: A sensor package comprises a sensor chip bonded to an intermediate carrier, with the sensor element over an opening in the carrier. The package is for soldering to a board, during which the intermediate carrier protects the sensor part of the sensor chip.

Abstract: An integrated circuit package for an integrated circuit having one or more sensor elements in a sensor element area of the circuit. An encapsulation covers bond wires but leaves an opening over the sensor element area. A protection layer is provided over the integrated circuit over which the encapsulation extends, and it has a channel around the sensor element area to act as a trap for any encapsulation material which has crept into the opening area.