Abstract: Vias for three dimensional (3D) stacking, packaging and heterogeneous integration of semi-conductor layers and wafers and a process for the manufacture of a via, to a via, to a 3D circuit and to a semiconductor device. Vias are interconnects used to vertically interconnect chips, devices, interconnection layers and wafers, i.e., in an out-of-plane direction.

Abstract: Vias for three dimensional (3D) stacking, packaging and heterogeneous integration of semi-conductor layers and wafers and a process for the manufacture of a via, to a via, to a 3D circuit and to a semiconductor device. Vias are interconnects used to vertically interconnect chips, devices, interconnection layers and wafers, i.e., in an out-of-plane direction.

Abstract: Thermally conductive polymer materials having thermally conductive charges and polymer network compositions characterized by the fact that the network is able to reorganize by exchange reactions that allow it to relax stresses and/or flow while maintaining network connectivity. As a result, the polymer network is characterized by its finite viscosity at elevated temperatures in spite of the crosslinking. These characteristics provide such materials remarkable properties for use as thermal interface and notably improved adhesion, self-repairing, in addition to greater processing flexibility, better mechanical properties, improved chemical resistance.