Patents by Inventor Henley Liu
Henley Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901338Abstract: An integrated circuit (IC) device is disclosed which includes at least a first hybrid bond interface layer disposed between adjacent wafers of a wafer stack. Routing within the hybrid bond interface layer allows test pads exposed on a top wafer of the wafer stack to electrically couple test keys within the wafer stack. By utilizing the routing within the hybrid bond interface layer to index electrical connections between adjacent wafers, IC dies stacked on the wafers may be fabricated with less mask sets as compared to conventional designs.Type: GrantFiled: October 29, 2021Date of Patent: February 13, 2024Assignee: XILINX, INC.Inventors: Myongseob Kim, Henley Liu, Cheang Whang Chang
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Publication number: 20240038556Abstract: Methods for mitigating warpage on stacked wafers are provided herein. In one example, a method for mitigating warpage on stacked wafers includes depositing a first warpage compensating layer on a backside of a first wafer, stacking an active side of the first wafer on an active side of a second wafer to form a wafer stack having circuitry of the first wafer electrically connected to circuitry of the second wafer, and removing the first warpage compensating layer from the backside of the first wafer prior dicing the wafer stack.Type: ApplicationFiled: July 27, 2022Publication date: February 1, 2024Inventors: Myongseob KIM, Henley LIU, Cheang-whang CHANG
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Publication number: 20230140675Abstract: An integrated circuit (IC) device is disclosed which includes at least a first hybrid bond interface layer disposed between adjacent wafers of a wafer stack. Routing within the hybrid bond interface layer allows test pads exposed on a top wafer of the wafer stack to electrically couple test keys within the wafer stack. By utilizing the routing within the hybrid bond interface layer to index electrical connections between adjacent wafers, IC dies stacked on the wafers may be fabricated with less mask sets as compared to conventional designs.Type: ApplicationFiled: October 29, 2021Publication date: May 4, 2023Inventors: Myongseob KIM, Henley LIU, Cheang Whang CHANG
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Patent number: 11355412Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.Type: GrantFiled: September 28, 2018Date of Patent: June 7, 2022Assignee: XILINX, INC.Inventors: Jaspreet Singh Gandhi, Gamal Refai-Ahmed, Henley Liu, Myongseob Kim, Tien-Yu Lee, Suresh Ramalingam, Cheang-Whang Chang
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Patent number: 11205639Abstract: An integrated circuit device and techniques for manufacturing the same are described therein. The integrated circuit device leverages two or more pairs of stacked integrated circuit dies that are fabricated in mirror images to reduce the complexity of manufacturing, thus reducing cost. In one example, an integrated circuit device is provided that includes an integrated circuit (IC) die stack. The IC die stack includes first, second, third and fourth IC dies. The first and second IC dies are coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other. The third and fourth IC dies are also coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other.Type: GrantFiled: February 21, 2020Date of Patent: December 21, 2021Assignee: XILINX, INC.Inventors: Myongseob Kim, Henley Liu, Cheang Whang Chang
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Patent number: 11114344Abstract: Integrated circuit (IC) dies and method for manufacturing the same are described herein that mitigate pattern loading effects during manufacture. In one example, the IC includes a die body having a first circuit block separated from an adjacent second circuit block by a buffer zone. The first and second circuit blocks have first and second transistors that are at least partially fabricated from a gate metal layer and disposed immediately adjacent the buffer zone. A dummy structure is formed in the buffer zone and is also at least partially fabricated from the gate metal layer. An amount of gate metal layer material in the dummy structure is selected to mitigate differences in the amount of gate metal layer material in regions of first and second circuit blocks that neighbor each other across the buffer zone.Type: GrantFiled: February 28, 2020Date of Patent: September 7, 2021Assignee: XILINX, INC.Inventors: Hui-Wen Lin, Nui Chong, Myongseob Kim, Henley Liu, Ping-Chin Yeh, Cheang-whang Chang
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Publication number: 20210265312Abstract: An integrated circuit device and techniques for manufacturing the same are described therein. The integrated circuit device leverages two or more pairs of stacked integrated circuit dies that are fabricated in mirror images to reduce the complexity of manufacturing, thus reducing cost. In one example, an integrated circuit device is provided that includes an integrated circuit (IC) die stack. The IC die stack includes first, second, third and fourth IC dies. The first and second IC dies are coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other. The third and fourth IC dies are also coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other.Type: ApplicationFiled: February 21, 2020Publication date: August 26, 2021Inventors: Myongseob KIM, Henley LIU, Cheang Whang CHANG
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Patent number: 11054461Abstract: Device(s) and method(s) related generally to a wafer or die stack are disclosed. In one such device, a die stack of two or more integrated circuit dies has associated therewith test circuits corresponding to each level of the die stack each with a set of pads. A test data-input path includes being from: a test data-in pad through a test circuit to a test data-out pad of each of the test circuits; and the test data-out pad to the test data-in pad between consecutive levels of the test circuits. Each of the set of pads includes the test data-in pad and the test data-out pad respectively thereof. A test data-output path is coupled to the test data-out pad of a level of the levels.Type: GrantFiled: March 12, 2019Date of Patent: July 6, 2021Assignee: XILINX, INC.Inventors: Nui Chong, Amitava Majumdar, Cheang-Whang Chang, Henley Liu, Myongseob Kim, Albert Shih-Huai Lin
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Patent number: 10971474Abstract: A chip package and method of fabricating the same are described herein. The chip package generally includes a stand-off which spaces a die from a substrate to control the collapse of a solder joint coupling the die to the substrate.Type: GrantFiled: March 1, 2019Date of Patent: April 6, 2021Assignee: XILINX, INC.Inventors: Jaspreet Singh Gandhi, Henley Liu
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Publication number: 20200303341Abstract: An electronic device and method for fabricating the same are disclosed herein. In one example the electronic device includes a substrate, a first die stack, and a second die stack. The first die stack includes a first functional die and a first dummy die. The first functional die is mounted to the substrate. The second stack includes a plurality of serially stacked second functional dies mounted to the substrate. The first dummy die is stacked on the first functional die. The first dummy die has a top surface that is substantially coplanar with a top surface of the second die stack. In one particular example, the first die stack includes a logic die and the second die stack includes a plurality of serially stacked memory dies.Type: ApplicationFiled: March 22, 2019Publication date: September 24, 2020Applicant: Xilinx, Inc.Inventors: Myongseob Kim, Henley Liu, Cheang-Whang Chang, Jaspreet Singh Gandhi
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Patent number: 10770430Abstract: An electronic device and method for fabricating the same are disclosed herein. In one example the electronic device includes a substrate, a first die stack, and a second die stack. The first die stack includes a first functional die and a first dummy die. The first functional die is mounted to the substrate. The second stack includes a plurality of serially stacked second functional dies mounted to the substrate. The first dummy die is stacked on the first functional die. The first dummy die has a top surface that is substantially coplanar with a top surface of the second die stack. In one particular example, the first die stack includes a logic die and the second die stack includes a plurality of serially stacked memory dies.Type: GrantFiled: March 22, 2019Date of Patent: September 8, 2020Assignee: XILINX, INC.Inventors: Myongseob Kim, Henley Liu, Cheang-Whang Chang, Jaspreet Singh Gandhi
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Patent number: 10720377Abstract: Examples described herein provide for an electronic device apparatus with multiple thermally conductive paths for heat dissipation. In an example, an electronic device apparatus includes a package comprising a die attached to a package substrate. The electronic device apparatus further includes a ring stiffener disposed around the die and on the package substrate, a heat sink disposed on the package, and a wedge disposed between the heat sink and the ring stiffener.Type: GrantFiled: November 9, 2018Date of Patent: July 21, 2020Assignee: XILINX, INC.Inventors: Gamal Refai-Ahmed, Ho Hyung Lee, Hui-Wen Lin, Henley Liu, Suresh Ramalingam
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Patent number: 10692837Abstract: A chip package assembly and method for fabricating the same are provided which utilize at least one modular core dice to reduce the cost of manufacture. The modular core dice include at least two die disposed on a wafer segment that are separated by a scribe lane. In one example, a chip package assembly is provided that includes an interconnect substrate stacked below a first wafer segment. The first wafer segment has a first die spaced from a second die by a first scribe lane. The interconnect substrate has conductive routing that is electrically connected to the first die and the second die through die connections.Type: GrantFiled: July 20, 2018Date of Patent: June 23, 2020Assignee: XILINX, INC.Inventors: Myongseob Kim, Henley Liu, Cheang-Whang Chang, Nui Chong
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Publication number: 20200152546Abstract: Examples described herein provide for an electronic device apparatus with multiple thermally conductive paths for heat dissipation. In an example, an electronic device apparatus includes a package comprising a die attached to a package substrate. The electronic device apparatus further includes a ring stiffener disposed around the die and on the package substrate, a heat sink disposed on the package, and a wedge disposed between the heat sink and the ring stiffener.Type: ApplicationFiled: November 9, 2018Publication date: May 14, 2020Applicant: Xilinx, Inc.Inventors: Gamal Refai-Ahmed, Ho Hyung Lee, Hui-Wen Lin, Henley Liu, Suresh Ramalingam
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Patent number: 10629512Abstract: A method and apparatus are provided that includes an integrated circuit die having an in-chip heat sink, along with an electronic device and a chip package having the same, and methods for fabricating the same. In one example, an integrated circuit die has an in-chip heat sink that separates a high heat generating integrated circuit from another integrated circuit disposed within the die. The in-chip heat sink provides a highly conductive heat transfer path from interior portions of the die to at least one exposed die surface.Type: GrantFiled: June 29, 2018Date of Patent: April 21, 2020Assignee: XILINX, INC.Inventors: Hong-Tsz Pan, Jonathan Chang, Nui Chong, Henley Liu, Gamal Refai-Ahmed, Suresh Ramalingam
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Publication number: 20200105642Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Applicant: Xilinx, Inc.Inventors: Jaspreet Singh Gandhi, Gamal Refai-Ahmed, Henley Liu, Myongseob Kim, Tien-Yu Lee, Suresh Ramalingam, Cheang-Whang Chang
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Patent number: 10593638Abstract: Methods and apparatus are described for enabling copper-to-copper (Cu—Cu) bonding at reduced temperatures (e.g., at most 200° C.) by significantly reducing Cu oxide formation. These techniques provide for faster cycle time and entail no extraordinary measures (e.g., forming gas). Such techniques may also enable longer queue (Q) or staging times. One example semiconductor structure generally includes a semiconductor layer, an adhesion layer disposed above the semiconductor layer, an anodic metal layer disposed above the adhesion layer, and a cathodic metal layer disposed above the anodic metal layer. An oxidation potential of the anodic metal layer may be greater than an oxidation potential of the cathodic metal layer. Such a semiconductor structure may be utilized in fabricating IC packages implementing 2.5D or 3D integration.Type: GrantFiled: March 29, 2017Date of Patent: March 17, 2020Assignee: XILINX, INC.Inventors: Jaspreet Singh Gandhi, Suresh Ramalingam, Henley Liu
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Patent number: 10527670Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.Type: GrantFiled: March 28, 2017Date of Patent: January 7, 2020Assignee: XILINX, INC.Inventors: Gamal Refai-Ahmed, Ivor G. Barber, Suresh Ramalingam, Jaspreet Singh Gandhi, Tien-Yu Lee, Henley Liu, David M. Mahoney, Mohsen H. Mardi
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Patent number: 10529645Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.Type: GrantFiled: June 8, 2017Date of Patent: January 7, 2020Assignee: XILINX, INC.Inventors: Jaspreet Singh Gandhi, Henley Liu, Tien-Yu Lee, Gamal Refai-Ahmed, Myongseob Kim, Ferdinand F. Fernandez, Ivor G. Barber, Suresh Ramalingam
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Publication number: 20200006186Abstract: A method and apparatus are provided that includes an integrated circuit die having an in-chip heat sink, along with an electronic device and a chip package having the same, and methods for fabricating the same. In one example, an integrated circuit die has an in-chip heat sink that separates a high heat generating integrated circuit from another integrated circuit disposed within the die. The in-chip heat sink provides a highly conductive heat transfer path from interior portions of the die to at least one exposed die surface.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Applicant: Xilinx, Inc.Inventors: Hong-Tsz Pan, Jonathan Chang, Nui Chong, Henley Liu, Gamal Refai-Ahmed, Suresh Ramalingam