Patents by Inventor Henning Braunisch

Henning Braunisch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10845552
    Abstract: An optoelectronic apparatus is presented. In embodiments, the apparatus may include a package including a substrate with a first side and a second side opposite the first side, wherein the first side comprises a ball grid array (BGA) field. The apparatus may further include one or more integrated circuits (ICs) disposed on the first side of the substrate, inside the BGA field, that thermally interface with a printed circuit board (PCB), to which the package is to be coupled, one or more optical ICs coupled to the second side and communicatively coupled with the one or more ICs via interconnects provided in the substrate, wherein at least one of the optical ICs is at least partially covered by an integrated heat spreader (IHS), to provide dissipation of heat produced by the at least one optical IC.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Henning Braunisch, Timothy A. Gosselin, Prasanna Raghavan, Yikang Deng, Zhiguo Qian
  • Patent number: 10845380
    Abstract: Embodiments of the invention include a microelectronic device having a sensing device and methods of forming the sensing device. In an embodiment, the sensing device includes a mass and a plurality of beams to suspend the mass. Each beam comprises first and second conductive layers and an insulating layer positioned between the first and second conductive layers to electrically isolate the first and second conductive layers. The first conductive layer is associated with drive signals and the second conductive layer is associated with sense signals of the sensing device.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Feras Eid, Henning Braunisch, Georgios C. Dogiamis, Sasha N. Oster
  • Publication number: 20200357747
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Henning BRAUNISCH, Chia-Pin CHIU, Aleksandar ALEKSOV, Hinmeng AU, Stefanie M. LOTZ, Johanna M. SWAN, Sujit SHARAN
  • Patent number: 10833020
    Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: November 10, 2020
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Kemal Aygun, Ajay Jain, Zhiguo Qian
  • Publication number: 20200350303
    Abstract: Embodiments described herein are directed to a thin film capacitor (TFC) for power delivery that is in situ in a package substrate and techniques of fabricating the TFC. In one example, the TFC includes a first electrode, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. Each of the dielectric layer and the second electrode comprises an opening. Furthermore, the two openings are positioned over one another such that the openings expose a surface of the first electrode. In this example, a first vertical interconnect access (via) is positioned on the exposed surface of the first electrode and a second via is positioned on an exposed surface of the second electrode. The TFC can be positioned in or on a layer of the package substrate close to a component (e.g., a die, a die stack, etc.) on the package substrate that may require a decoupling capacitance.
    Type: Application
    Filed: May 1, 2019
    Publication date: November 5, 2020
    Inventors: Thomas SOUNART, Aleksandar ALEKSOV, Henning BRAUNISCH
  • Patent number: 10819445
    Abstract: Embodiments may relate to a transceiver chip. The transceiver chip may include a substrate that has a first transceiver component and a second transceiver component positioned therein. The transceiver chip may further include a well material that is positioned between the first transceiver component and the second transceiver component. The well material may mitigate cross-talk between the first transceiver component and the second transceiver component. Other embodiments may be described or claimed.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 27, 2020
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Georgios Dogiamis, Henning Braunisch, Hyung-Jin Lee, Richard Dischler
  • Publication number: 20200312796
    Abstract: An inductor in a device package and a method of forming the inductor in the device package are described. The inductor includes a first conductive layer disposed on a substrate. The inductor also has one or more hybrid magnetic additively manufactured (HMAM) layers disposed over and around the first conductive layer to form one or more via openings over the first conductive layer. The inductor further includes one or more vias disposed into the one or more via openings, wherein the one or more vias are only disposed on the portions of the exposed first conductive layer. The inductor has a dielectric layer disposed over and around the one or more vias, the HMAM layers, and the substrate. The inductor also has a second conductive layer disposed over the one or more vias and the dielectric layer.
    Type: Application
    Filed: September 30, 2017
    Publication date: October 1, 2020
    Inventors: Henning BRAUNISCH, Feras EID, Georgios C. DOGIAMIS
  • Publication number: 20200312782
    Abstract: A device package and a method of forming the device package are described. The device package includes a substrate having a ground plane and dies disposed on the substrate. The dies are electrically coupled to the substrate with solder balls or bumps surrounded by an underfill layer. The device package has a mold layer disposed over and around the dies, the underfill layer, and the substrate. The device package further includes an additively manufactured electromagnetic interference (EMI) shield layer disposed on an outer surface of the mold layer. The additively manufactured EMI shield layer is electrically coupled to the ground plane of the substrate. The outer surface of the mold layer may include a topmost surface and one or more sidewalls that are covered with the additively manufactured EMI shield layer. The additively manufactured EMI shield may include a first and second additively manufactured EMI shield layers and an additively manufactured EMI shield frame.
    Type: Application
    Filed: September 30, 2017
    Publication date: October 1, 2020
    Inventors: Feras EID, Henning BRAUNISCH, Shawna M. LIFF, Georgios C. DOGIAMIS, Johanna M. SWAN
  • Publication number: 20200315052
    Abstract: Embodiments may relate an electronic device that includes a first platform and a second platform coupled with a chassis. The platforms may include respective microelectronic packages. The electronic device may further include a waveguide coupled to the first platform and the second platform such that their respective microelectronic packages are communicatively coupled by the waveguide. Other embodiments may be described or claimed.
    Type: Application
    Filed: May 2, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Telesphor Kamgaing, Johanna M. Swan, Georgios Dogiamis, Henning Braunisch, Adel A. Elsherbini, Aleksandar Aleksov, Richard Dischler
  • Publication number: 20200303328
    Abstract: Embodiments may relate to a multi-chip microelectronic package that includes a first die and a second die coupled to a package substrate. The first and second dies may have respective radiative elements that are communicatively coupled with one another such that they may communicate via an electromagnetic signal with a frequency at or above approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.
    Type: Application
    Filed: April 25, 2019
    Publication date: September 24, 2020
    Applicant: Intel Corporation
    Inventors: Henning Braunisch, Adel A. Elsherbini, Georgios Dogiamis, Telesphor Kamgaing, Richard Dischler, Johanna M. Swan, Victor J. Prokoff
  • Publication number: 20200303327
    Abstract: Embodiments may relate to a microelectronic package that includes a substrate signal path and a waveguide. The package may further include dies that are communicatively coupled with one another by the substrate signal path and the waveguide. The substrate signal path may carry a signal with a frequency that is different than the frequency of a signal that is to be carried by the waveguide. Other embodiments may be described or claimed.
    Type: Application
    Filed: April 25, 2019
    Publication date: September 24, 2020
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Georgios Dogiamis, Johanna M. Swan, Aleksandar Aleksov, Telesphor Kamgaing, Henning Braunisch
  • Publication number: 20200304171
    Abstract: Embodiments may relate to a baseband module with communication pathways for a first data signal and a second data signal. The baseband module may also include a finite impulse response (FIR) filter in a communication path between the first signal input and the second signal output. Other embodiments may be described or claimed.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Applicant: Intel Corporation
    Inventors: Henning Braunisch, Georgios Dogiamis, Diego Correas-Serrano, Neelam Prabhu-Gaunkar, Telesphor Kamgaing, Cooper S. Levy, Chintan S. Thakkar, Stefano Pellerano
  • Publication number: 20200304215
    Abstract: Embodiments may relate to a communications module comprising with a dispersion compensation module communicatively coupled between a baseband module and a radio frequency (RF) module. The dispersion compensation module may be configured to process a data signal at an intermediate frequency that is between a baseband frequency and a RF frequency. Other embodiments may be described or claimed.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Applicant: Intel Corporation
    Inventors: Diego Correas-Serrano, Georgios Dogiamis, Henning Braunisch, Neelam Prabhu-Gaunkar, Telesphor Kamgaing, Thomas W. Brown, Stefano Pellerano
  • Publication number: 20200303329
    Abstract: Embodiments may relate to a microelectronic package that includes a radio frequency (RF) chip coupled with a die by interconnects with a first pitch. The RF chip may further be coupled with a waveguide of a package substrate by interconnects with a second pitch that is different than the first pitch. The RF chip may facilitate conveyance of data to the waveguide as an electromagnetic signal with a frequency greater than approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.
    Type: Application
    Filed: April 29, 2019
    Publication date: September 24, 2020
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Georgios Dogiamis, Telesphor Kamgaing, Henning Braunisch, Johanna M. Swan, Shawna M. Liff, Aleksandar Aleksov
  • Publication number: 20200294940
    Abstract: Embodiments may relate to a semiconductor package that includes a package substrate coupled with a die. The package may further include a waveguide coupled with the first package substrate. The waveguide may include two or more layers of a dielectric material with a waveguide channel positioned between two layers of the two or more layers of the dielectric material. The waveguide channel may convey an electromagnetic signal with a frequency greater than 30 gigahertz (GHz). Other embodiments may be described or claimed.
    Type: Application
    Filed: April 29, 2019
    Publication date: September 17, 2020
    Applicant: Intel Corporation
    Inventors: Georgios Dogiamis, Aleksandar Aleksov, Adel A. Elsherbini, Henning Braunisch, Johanna M. Swan, Telesphor Kamgaing
  • Publication number: 20200296823
    Abstract: Embodiments may relate to an electronic module for use in an electronic device. The electronic module may include a printed circuit board (PCB) with a first die and a second die. A waveguide channel may be communicatively coupled with the first die and the second die and configured to convey an electromagnetic signal from the first die to the second die. In embodiments, the electromagnetic signal may have a frequency greater than 30 gigahertz (GHz). Other embodiments may be described or claimed.
    Type: Application
    Filed: April 30, 2019
    Publication date: September 17, 2020
    Applicant: Intel Corporation
    Inventors: Telesphor Kamgaing, Johanna M. Swan, Georgios Dogiamis, Henning Braunisch, Adel A. Elsherbini, Aleksandar Aleksov
  • Patent number: 10763216
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Hinmeng Au, Stefanie M. Lotz, Johanna M. Swan, Sujit Sharan
  • Publication number: 20200273839
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.
    Type: Application
    Filed: December 29, 2017
    Publication date: August 27, 2020
    Inventors: Adel A. ELSHERBINI, Henning BRAUNISCH, Aleksandar ALEKSOV, Shawna M. LIFF, Johanna M. SWAN, Patrick MORROW, Kimin JUN, Brennen MUELLER, Paul B. FISCHER
  • Publication number: 20200273824
    Abstract: Embodiments may relate to a microelectronic package that includes a package substrate and a signal interconnect coupled with the face of the package substrate. The microelectronic package may further include a ground interconnect coupled with the face of the package substrate. The ground interconnect may at least partially surround the signal interconnect. Other embodiments may be described or claimed.
    Type: Application
    Filed: March 29, 2019
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Telesphor Kamgaing, Georgios Dogiamis, Hyung-Jin Lee, Henning Braunisch, Richard Dischler
  • Patent number: 10734236
    Abstract: Embodiments include devices and methods, including a method for processing a substrate. The method includes providing a substrate including a first portion and a second portion, the first portion including a feature, the feature including an electrically conductive region, the second portion including a dielectric surface region. The method also includes performing self-assembled monolayer (SAM) assisted structuring plating to form a structure comprising a metal on the dielectric surface region, the feature being formed using a process other than the SAM assisted structuring plating used to form the structure, and the structure being formed after the feature. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: August 4, 2020
    Assignee: INTEL CORPORATION
    Inventors: Sasha N. Oster, Fay Hua, Telesphor Kamgaing, Adel A. Elsherbini, Henning Braunisch, Johanna M. Swan