Patents by Inventor Henning Braunisch

Henning Braunisch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200168553
    Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.
    Type: Application
    Filed: January 28, 2020
    Publication date: May 28, 2020
    Inventors: Henning Braunisch, Kemal Aygun, Ajay Jain, Zhiguo Qian
  • Patent number: 10651525
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
  • Patent number: 10645813
    Abstract: A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Brandon M. Rawlings, Henning Braunisch
  • Patent number: 10623106
    Abstract: Embodiments herein may relate to an interconnect that includes a transceiver, where the transceiver is configured to receive a data stream, convert the data stream to a quadrature amplitude modulation (QAM) mapping/shaping signal, where the QAM mapping/shaping signal is a frequency component of the data stream, convert the QAM mapping/shaping signal to a Hilbert transform signal, where the Hilbert transform signal includes a reverse order of an in-phase component of the QAM mapping/shaping signal and a reverse order of a quadrature component of the QAM mapping/shaping signal, convert the Hilbert transform signal to a QAM mapping/shaping signal, where the QAM mapping/shaping signal is a single sideband (SSB) time domain mm wave signal, where the SSB time domain mm wave signal is the Hilbert transform signal converted to a time domain signal, and communicate the SSB time domain mm wave signal over a waveguide using a waveguide interconnect.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Hyung-Jin Lee, Cho-ying Lu, Henning Braunisch, Telesphor Kamgaing, Georgios Dogiamis, Richard Dischler
  • Publication number: 20200075493
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Application
    Filed: November 7, 2019
    Publication date: March 5, 2020
    Inventors: Henning BRAUNISCH, Chia-Pin CHIU, Aleksandar ALEKSOV, Hinmeng AU, Stefanie M. LOTZ, Johanna M. SWAN, Sujit SHARAN
  • Publication number: 20200021330
    Abstract: Technology for simplified multimode signaling includes determining first and second self ?-terms, cross coupling ?-terms, and a delay skew term. For each communication link bundled in groups, the signals can be modulated as a superposition of the signals delayed and weighted based on the first and second self ?-terms, the cross coupling ?-terms and the delay skew term.
    Type: Application
    Filed: March 1, 2017
    Publication date: January 16, 2020
    Applicant: Intel Corporation
    Inventors: Yidnekachew S. Mekonnen, Kemal Aygun, Henning Braunisch
  • Publication number: 20200006236
    Abstract: Embodiments may relate to an interposer that has a first layer with a plurality of first layer pads that may couple with a die. The interposer may further include a second layer with a power delivery component. The interposer may further include a very high density (VHD) layer, that has a VHD pad coupled by a first via with the power delivery component and coupled by a second via with a first layer pad. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Andrew Paul Collins, Jianyong Xie, Sujit Sharan, Henning Braunisch, Aleksandar Aleksov
  • Publication number: 20200006258
    Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Aleksandar ALEKSOV, Thomas SOUNART, Kristof DARMAWIKARTA, Henning BRAUNISCH, Prithwish CHATTERJEE, Andrew J. BROWN
  • Patent number: 10510669
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 17, 2019
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Hinmeng Au, Stefanie M. Lotz, Johanna M. Swan, Sujit Sharan
  • Publication number: 20190356033
    Abstract: Disclosed herein are various designs for dielectric waveguides, as well as methods of manufacturing such waveguides. One type of dielectric waveguides described herein includes waveguides with one or more cavities in the dielectric waveguide material. Another type of dielectric waveguides described herein includes waveguides with a conductive ridge in the dielectric waveguide material. Dielectric waveguides described herein may be dispersion reduced dielectric waveguides, compared to conventional dielectric waveguides, and may be designed to adjust the difference in the group delay between the lower frequencies and the higher frequencies of a chosen bandwidth.
    Type: Application
    Filed: June 21, 2018
    Publication date: November 21, 2019
    Applicant: Intel Corporation
    Inventors: Georgios Dogiamis, Adel A. Elsherbini, Telesphor Kamgaing, Henning Braunisch, Johanna M. Swan
  • Patent number: 10475736
    Abstract: Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Arnab Sarkar, Arghya Sain, Kristof Darmawikarta, Henning Braunisch, Prashant D. Parmar, Sujit Sharan, Johanna M. Swan, Feras Eid
  • Publication number: 20190318993
    Abstract: A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.
    Type: Application
    Filed: December 28, 2016
    Publication date: October 17, 2019
    Inventors: Ravindranath V. Mahajan, Zhiguo Qian, Henning Braunisch, Kemal Aygun, Sujit Sharan
  • Publication number: 20190317285
    Abstract: An optoelectronic apparatus is presented. In embodiments, the apparatus may include a package including a substrate with a first side and a second side opposite the first side, wherein the first side comprises a ball grid array (BGA) field. The apparatus may further include one or more integrated circuits (ICs) disposed on the first side of the substrate, inside the BGA field, that thermally interface with a printed circuit board (PCB), to which the package is to be coupled, one or more optical ICs coupled to the second side and communicatively coupled with the one or more ICs via interconnects provided in the substrate, wherein at least one of the optical ICs is at least partially covered by an integrated heat spreader (IHS), to provide dissipation of heat produced by the at least one optical IC.
    Type: Application
    Filed: September 12, 2017
    Publication date: October 17, 2019
    Inventors: Shawna M. LIFF, Henning BRAUNISCH, Timothy A. GOSSELIN, Prasanna RAGHAVAN, Yikang DENG, Zhiguo QIAN
  • Publication number: 20190259622
    Abstract: Embodiments include devices and methods, including a method for processing a substrate. The method includes providing a substrate including a first portion and a second portion, the first portion including a feature, the feature including an electrically conductive region, the second portion including a dielectric surface region. The method also includes performing self-assembled monolayer (SAM) assisted structuring plating to form a structure comprising a metal on the dielectric surface region, the feature being formed using a process other than the SAM assisted structuring plating used to form the structure, and the structure being formed after the feature. Other embodiments are described and claimed.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Inventors: Sasha N. OSTER, Fay HUA, Telesphor KAMGAING, Adel A. ELSHERBINI, Henning BRAUNISCH, Johanna M. SWAN
  • Publication number: 20190259705
    Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.
    Type: Application
    Filed: September 30, 2016
    Publication date: August 22, 2019
    Inventors: Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Henning Braunisch, Krishna Bharath, Javier Soto Gonzalez, Javier A. Falcon
  • Publication number: 20190252322
    Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.
    Type: Application
    Filed: June 30, 2016
    Publication date: August 15, 2019
    Inventors: Henning Braunisch, Kemel Aygun, Ajay Jain, Zhiguo Qian
  • Publication number: 20190252321
    Abstract: Disclosed is a signaling system. The signaling system may comprise a transmitter, a receiver, and a package interconnect. The transmitter may be configured to transmit M signals. The receiver may be configured to receive the M signals. The package interconnect may include a bundle of N wires electrically connecting the transmitter and the receiver. During operation, the N wires may be electromagnetically coupled with each other and the M signals may travel between the transmitter and the receiver on the bundle of N wires.
    Type: Application
    Filed: September 28, 2016
    Publication date: August 15, 2019
    Inventors: Henning Braunisch, Kemal Aygun, Yidnekachew S. Mekonnen
  • Patent number: 10381291
    Abstract: Embodiments of the invention include conductive vias and methods for forming the conductive vias. In one embodiment, a via pad is formed over a first dielectric layer and a photoresist layer is formed over the first dielectric layer and the via pad. Embodiments may then include patterning the photoresist layer to form a via opening over the via pad and depositing a conductive material into the via opening to form a via over the via pad. Embodiments may then includeremoving the photoresist layer and forming a second dielectric layer over the first dielectric layer, the via pad, and the via. For example a top surface of the second dielectric layer is formed above a top surface of the via in some embodiments. Embodiments may then include recessing the second dielectric layer to expose a top portion of the via.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Henning Braunisch, Brandon M. Rawlings, Aleksandar Aleksov, Feras Eid, Javier Soto
  • Patent number: 10361142
    Abstract: An apparatus including a die, a first side of the die including a first type of system level contact points and a second side including a second type of contact points; and a package substrate coupled to the die and the second side of the die. An apparatus including a die, a first side of the die including a plurality of system level logic contact points and a second side including a second plurality of system level power contact points. A method including coupling one of a first type of system level contact points on a first side of a die and a second type of system level contact points on a second side of the die to a package substrate.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: July 23, 2019
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Feras Eid, Adel A. Elsherbini, Johanna M. Swan, Don W. Nelson
  • Patent number: 10304686
    Abstract: Embodiments include devices and methods, including a method for processing a substrate. The method includes providing a substrate including a first portion and a second portion, the first portion including a feature, the feature including an electrically conductive region, the second portion including a dielectric surface region. The method also includes performing self-assembled monolayer (SAM) assisted structuring plating to form a structure comprising a metal on the dielectric surface region, the feature being formed using a process other than the SAM assisted structuring plating used to form the structure, and the structure being formed after the feature. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 28, 2019
    Assignee: INTEL CORPORATION
    Inventors: Sasha N. Oster, Fay Hua, Telesphor Kamgaing, Adel A. Elsherbini, Henning Braunisch, Johanna M. Swan