Patents by Inventor Henning Braunisch

Henning Braunisch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DUAL-SIDED DIE PACKAGES
    Publication number: 20170287808
    Abstract: An apparatus including a die, a first side of the die including a first type of system level contact points and a second side including a second type of contact points; and a package substrate coupled to the die and the second side of the die. An apparatus including a die, a first side of the die including a plurality of system level logic contact points and a second side including a second plurality of system level power contact points. A method including coupling one of a first type of system level contact points on a first side of a die and a second type of system level contact points on a second side of the die to a package substrate.
    Type: Application
    Filed: June 16, 2017
    Publication date: October 5, 2017
    Inventors: Henning BRAUNISCH, Feras EID, Adel A. ELSHERBINI, Johanna M. SWAN, Don W. NELSON
  • ZERO-MISALIGNMENT VIA-PAD STRUCTURES
    Publication number: 20170280568
    Abstract: A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.
    Type: Application
    Filed: June 13, 2017
    Publication date: September 28, 2017
    Inventors: Brandon M. Rawlings, Henning Braunisch
  • Dual-sided die packages
    Patent number: 9711428
    Abstract: An apparatus including a die, a first side of the die including a first type of system level contact points and a second side including a second type of contact points; and a package substrate coupled to the die and the second side of the die. An apparatus including a die, a first side of the die including a plurality of system level logic contact points and a second side including a second plurality of system level power contact points. A method including coupling one of a first type of system level contact points on a first side of a die and a second type of system level contact points on a second side of the die to a package substrate.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: July 18, 2017
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Feras Eid, Adel A. Elsherbini, Johanna M. Swan, Don W. Nelson
  • Zero-misalignment via-pad structures
    Patent number: 9713264
    Abstract: A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: July 18, 2017
    Assignee: Intel Corporation
    Inventors: Brandon M. Rawlings, Henning Braunisch
  • Shielded bundle interconnect
    Publication number: 20170187419
    Abstract: Embodiments are generally directed to a shielded bundle interconnect. An embodiment of an apparatus includes multiple signal bundles, the signal bundles including a first signal bundle including a first plurality of signals and a second signal bundle including a second plurality of signals; and a lithographic via shielding to provide electromagnetic shielding, the lithographic via shielding located at least in part between the first signal bundle and the second signal bundle, wherein the lithographic via shielding includes at least a via generated by a lithographic via process. The lithographic via shielding partially or completely surrounds at least one of the signal bundles of the apparatus.
    Type: Application
    Filed: December 26, 2015
    Publication date: June 29, 2017
    Inventors: Yu Zhang, Mathew J. Manusharow, Adel A. Elsherbini, Henning Braunisch, Kemal Aygun
  • OPTICAL I/O SYSTEM USING PLANAR LIGHT-WAVE INTEGRATED CIRCUIT
    Publication number: 20170131469
    Abstract: Photonic components are placed on the processor package to bring the optical signal close to the processor die. The processor package includes a substrate to which the processor die is coupled, and which allows the processor die to connect to a printed circuit board. The processor package also includes transceiver logic, electrical-optical conversion circuits, and an optical coupler. The electrical-optical conversion circuits can include laser(s), modulator(s), and photodetector(s) to transmit and receive and optical signal. The coupler interfaces to a fiber that extends off the processor package. Multiple fibers can be brought to the processor package allowing for a scalable high-speed, high-bandwidth interconnection to the processor.
    Type: Application
    Filed: November 15, 2016
    Publication date: May 11, 2017
    Inventors: Mauro J. Kobrinsky, Henning Braunisch, Shawna M. Liff, Peter L. Chang, Bruce A. Block, Johanna M. Swan
  • Low Loss and Low Cross Talk Transmission Lines using Shaped Vias
    Publication number: 20170093007
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: Adel A. ELSHERBINI, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
  • PACKAGE INTEGRATED POWER INDUCTORS USING LITHOGRAPHICALLY DEFINED VIAS
    Publication number: 20170092412
    Abstract: Embodiments of the invention include inductors integrated into a package substrate that have increased thicknesses due to the use of shaped vias, and methods of forming such packages. In an embodiment of the invention an inductor may be formed in a package substrate may include a first inductor line formed on the package substrate. In some embodiments, a shaped via may be formed over the first inductor line. Additional embodiments may include a dielectric layer that is formed over the package substrate, the first inductor line and around the shaped via. In one embodiment, a second inductor line may also be formed over the shaped via. Some embodiments of the invention may include an inductor that is a spiral inductor.
    Type: Application
    Filed: September 26, 2015
    Publication date: March 30, 2017
    Inventors: Mathew J. Manusharow, Yonggang Li, William J. Lambert, Krishna Bharath, Adel A. Elsherbini, Feras Eid, Aleksandar Aleksov, Henning Braunisch
  • Optical I/O system using planar light-wave integrated circuit
    Patent number: 9507086
    Abstract: Photonic components are placed on the processor package to bring the optical signal close to the processor die. The processor package includes a substrate to which the processor die is coupled, and which allows the processor die to connect to a printed circuit board. The processor package also includes transceiver logic, electrical-optical conversion circuits, and an optical coupler. The electrical-optical conversion circuits can include laser(s), modulator(s), and photodetector(s) to transmit and receive and optical signal. The coupler interfaces to a fiber that extends off the processor package. Multiple fibers can be brought to the processor package allowing for a scalable high-speed, high-bandwidth interconnection to the processor.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: November 29, 2016
    Inventors: Mauro J. Kobrinsky, Henning Braunisch, Shawna M. Liff, Peter L. Chang, Bruce A. Block, Johanna M. Swan
  • Optical connection techniques and configurations
    Patent number: 9435967
    Abstract: Embodiments of the present disclosure provide optical connection techniques and configurations. In one embodiment, an apparatus includes a receptacle for mounting on a surface of a package substrate, the receptacle having a pluggable surface to receive an optical coupler plug such that the optical coupler plug is optically aligned with one or more optical apertures of an optoelectronic assembly that is configured to emit and/or receive light using the one or more optical apertures in a direction that is substantially perpendicular to the surface of the package substrate when the optoelectronic assembly is affixed to the package substrate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: September 6, 2016
    Assignee: INTEL CORPORATION
    Inventors: Henning Braunisch, Shawna M. Liff, Peter L. Chang
  • DUAL-SIDED DIE PACKAGES
    Publication number: 20160211190
    Abstract: An apparatus including a die, a first side of the die including a first type of system level contact points and a second side including a second type of contact points; and a package substrate coupled to the die and the second side of the die. An apparatus including a die, a first side of the die including a plurality of system level logic contact points and a second side including a second plurality of system level power contact points. A method including coupling one of a first type of system level contact points on a first side of a die and a second type of system level contact points on a second side of the die to a package substrate.
    Type: Application
    Filed: September 27, 2013
    Publication date: July 21, 2016
    Inventors: Henning BRAUNISCH, Feras EID, Adel A. ELSHERBINI, Johanna M. SWAN, Don W. NELSON
  • Thermal management in packaged VCSELs
    Patent number: 9391427
    Abstract: Heat management systems for vertical cavity surface emitting laser (VCSEL) chips are provided. Embodiments of the invention provide substrates having a vertical cavity surface emitting laser chip disposed on the substrate surface and electrically interconnected with the substrate, a thermal frame disposed on the substrate surface and proximate to at least three sides of the vertical cavity surface emitting laser chip, and a thermal interface material disposed between the at least three sides of the vertical cavity surface emitting laser chip and the thermal frame. The substrate can also include a transceiver chip that is operably coupled to a further integrated circuit chip and that is capable of driving the VCSEL chip.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: July 12, 2016
    Assignee: INTEL CORPORATION
    Inventors: Feras Eid, Shawna M. Liff, Henning Braunisch
  • Zero-Misalignment Via-Pad Structures
    Publication number: 20160183370
    Abstract: A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 23, 2016
    Inventors: Brandon M. Rawlings, Henning BRAUNISCH
  • OPTICAL CONNECTION TECHNIQUES AND CONFIGURATIONS
    Publication number: 20160124166
    Abstract: Embodiments of the present disclosure provide optical connection techniques and configurations. In one embodiment, an apparatus includes a receptacle for mounting on a surface of a package substrate, the receptacle having a pluggable surface to receive an optical coupler plug such that the optical coupler plug is optically aligned with one or more optical apertures of an optoelectronic assembly that is configured to emit and/or receive light using the one or more optical apertures in a direction that is substantially perpendicular to the surface of the package substrate when the optoelectronic assembly is affixed to the package substrate. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: January 11, 2016
    Publication date: May 5, 2016
    Inventors: Henning Braunisch, Shawna M. Liff, Peter L. Chang
  • Optical connection techniques and configurations
    Patent number: 9310553
    Abstract: Embodiments of the present disclosure provide optical connection techniques and configurations. In one embodiment, an apparatus includes a receptacle for mounting on a surface of a package substrate, the receptacle having a pluggable surface to receive an optical coupler plug such that the optical coupler plug is optically aligned with one or more optical apertures of an optoelectronic assembly that is configured to emit and/or receive light using the one or more optical apertures in a direction that is substantially perpendicular to the surface of the package substrate when the optoelectronic assembly is affixed to the package substrate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: April 12, 2016
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Shawna M. Liff, Peter L. Chang
  • Electro-optical assembly including a glass bridge
    Patent number: 9250406
    Abstract: Embodiments of the present disclosure provide techniques and configurations for routing signals of an electro-optical assembly using a glass bridge. In one embodiment, an electro-optical assembly includes a laser die having a laser device and a glass bridge electrically coupled with the laser die by one or more interconnect structures, the glass bridge including electrical routing features configured to route electrical signals to the laser die from a transmitter device. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: February 2, 2016
    Assignee: Intel Corporation
    Inventors: Peter L. D. Chang, Edris M. Mohammed, Henning Braunisch, Hengju Cheng
  • Integrated inductor structure and method of fabrication
    Patent number: 9153547
    Abstract: An inductor structure comprised of a magnetic section and a single turn solenoid. The single turn solenoid to contain within a portion of the magnetic section and circumscribed by the magnetic section.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventors: Ankur Mohan Crawford, Henning Braunisch, Rajendran Nair, Gilroy Vandentop, Shan X. Wang
  • Magnetic core inductor (MCI) structures for integrated voltage regulators
    Patent number: 9129817
    Abstract: Semiconductor packages including magnetic core inductor (MCI) structures for integrated voltage regulators are described. In an example, a semiconductor package includes a package substrate and a semiconductor die coupled to a first surface of the package substrate. The semiconductor die has a first plurality of metal-insulator-metal (MIM) capacitor layers thereon. The semiconductor package also includes a magnetic core inductor (MCI) die coupled to a second surface of the package substrate. The MCI die includes one or more slotted inductors and has a second plurality of MIM capacitor layers thereon.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 8, 2015
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Kevin P. O'Brien, Henning Braunisch, Krishna Bharath
  • Matrix matching crosstalk reduction device and method
    Patent number: 9093990
    Abstract: This disclosure relates generally to devices, systems, and methods that include conductive lines configured to transmit electrical signals between a first electronic component and a second electronic component between which the conductive lines are coupled. The devices, systems, and methods further include a transmitter, configured to generate the electrical signals, the transmitter including a source impedance based, at least in part, on a resistive coupling between individual ones of the conductive lines, a source impedance matrix of the source impedance being substantially proportional to the characteristic impedance matrix of the plurality of conductive lines.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: July 28, 2015
    Assignee: Intel Corporation
    Inventor: Henning Braunisch
  • MATRIX MATCHING CROSSTALK REDUCTION DEVICE AND METHOD
    Publication number: 20150077157
    Abstract: This disclosure relates generally to devices, systems, and methods that include conductive lines configured to transmit electrical signals between a first electronic component and a second electronic component between which the conductive lines are coupled. The devices, systems, and methods further include a transmitter, configured to generate the electrical signals, the transmitter including a source impedance based, at least in part, on a resistive coupling between individual ones of the conductive lines, a source impedance matrix of the source impedance being substantially proportional to the characteristic impedance matrix of the plurality of conductive lines.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 19, 2015
    Inventor: Henning Braunisch