Abstract: A wireless-local area network access point (101, 102; 800; 1100) sends at least one wake-up packet for activating broadcasting devices (21, 22, 23, 24) in vicinity of the wireless-local area network access point (101, 102; 800; 1100). In response to the at least one wake-up packet, the wireless-local area network access point (101, 102; 800; 1100) receives responses from the broadcasting devices (21, 22, 23, 24). Each response comprises an identifier of the broadcasting device (21, 22, 23, 24) sending the response. The at least one wake-up packet coordinates the sending of the responses by the broadcasting devices (21, 22, 23, 24) with respect to each other.

Abstract: An oscillator circuit (15) is disclosed. It comprises N amplifier circuits (A1-A4), connected in a ring and has a first and a second supply terminal (s1, s2). Each amplifier circuit (A1-A4) comprises an input transistor (M1) having its gate connected to the input (in) of the amplifier circuit, its drain connected to an internal node (x) of the amplifier circuit, and its source connected to the first supply terminal (si). Furthermore, each amplifier circuit (A1-A4) comprises a first resonance circuit (R1) comprising a first inductor (Ls) and a first capacitor (Cs), wherein the first inductor (Ls) is connected between the internal node (x) and the output (out) of the amplifier circuit, and the first capacitor (Cs) is connected between the output (out) of the amplifier circuit and one of the first and the second supply terminals (s1, s2).

Abstract: A method for a wake-up transmitter comprises generating a wakeup signal (WUS) from a digital WUS sequence having an information symbol rate and a corresponding information symbol bandwidth, and transmitting the WUS over a frequency range having a signal bandwidth, wherein the signal bandwidth is larger than twice the information symbol rate, and wherein any frequency interval comprised in the frequency range conveys the digital WUS sequence when a width of the frequency interval is at least the information symbol bandwidth. A corresponding method for a wake-up receiver comprises receiving the WUS over the frequency range, and filtering the received WUS through a filter having a filter bandwidth for passing the information symbol bandwidth of the received WUS. Corresponding apparatuses, wake-up transmitter, wake-up receiver, communication device and computer program product are also disclosed.

Abstract: A wireless device comprises at least one antenna and a main receiver, having first automatic gain control circuitry for controlling a gain applied to signals received by means of the antenna. The wireless device further comprises an auxiliary receiver, configured to monitor a power of a periodic reference signal received by means of the antenna, and further configured to send power information to the main receiver. The main receiver is configured, on waking up, to use the power information received from the auxiliary receiver to assist in operation of the first automatic gain control circuitry.

Abstract: On-chip Multi-band equalizers for adjusting signal strength for a receiver receiving multi-band frequency signals are provided, The multi-band equalizer comprises multiple series connected tapped LC resonators. The tapped LC resonator may be capacitive tapping or inductive tapping, where both frequency and gain of the frequency bands of interest may be programmed by tuning the capacitances of the programmable capacitors and/or selecting the tapped out terminals of the inductors. The multi-band equalizer may be connected to a signal node, for instance between two amplifiers in the receiver.

Abstract: A radio receiver comprises a local oscillator arrangement and a controller. The local oscillator arrangement is arranged to provide a signal for down-conversion of radio frequency signal to an intermediate frequency or a baseband frequency in the radio receiver, and the local oscillator arrangement is capable of selectably providing multiple frequency generation qualities. The controller is arranged to estimate a tolerable frequency generation quality for the current operation of the radio receiver or determine whether the current operation of the radio receiver is satisfactory in sense of a currently provided frequency generation quality, and based on the estimation or determination adjust frequency generation quality of the local oscillator arrangement by selecting one of the multiple frequency generation qualities. A radio arrangement, a method and a computer program are also disclosed.

Abstract: A method of establishing connection between a first node in a wireless network and a second node in said wireless network, wherein each of said first and second nodes comprise a primary radio receiver and a wake up receiver, each of said nodes comprising a Radio Frequency, RF, switch, arranged to connect one of said primary or secondary radios to a radio antenna, said method comprising the steps of transmitting, by said first node, to a wake-up receiver of a second radio node, a wake-up signal that indicates a frequency channel on which the second radio node is to transmit a response, receiving, by said first node, in response to transmitting said wake-up signal, response from said second radio node on the frequency channel indicated, and establishing, by said first node, a connection between said first and second nodes in order to transfer data between said first and second nodes. The present disclosure also relates to corresponding mesh nodes and a computer program product.

Abstract: A digital-to-analog conversion circuit (60) for converting a digital input sequence to an analog representation is disclosed. It comprises a first DAC, (100) wherein the first DAC (100) is of a capacitive voltage division type having a capacitive load (110). Furthermore, it comprises a second DAC (120) having a resistive load (130). An output (104) of the first DAC (100) and an output (124) of the second DAC (120) are connected, such that said capacitive load (110) and said resistive load (130) are connected in parallel.

Abstract: A frequency detector (200) and method therein for measuring and tuning a frequency of a controlled oscillator are disclosed. The frequency detector (200) comprises a pulse generator (210) for generating sampling pulses; a sample circuitry (220) for sampling output states of the controlled oscillator (180); and a digital processing unit (230). The sample circuitry (220) is configured to sub-sample the output states of the controlled oscillator (180) at two or more sampling frequencies, and all sampling frequencies are lower than the frequency of the controlled oscillator. The digital processing unit (230) is configured to calculate a frequency offset of the oscillator based on the sampled states and generate a control signal based on the frequency offset to tune the frequency of the oscillator.

Abstract: An integrated transformer arrangement for combining output signals of multiple differential power amplifiers to a single-ended load. The integrated transformer arrangement comprises a first transformer branch comprising an inductor loop. The inductor loop comprises a set of N windings connected in series. The first transformer branch further comprises a number of primary inductors. Each primary inductor comprises a winding placed concentrically to one winding of the inductor loop, and each primary inductor is configured to couple to a differential output of one of the multiple differential power amplifiers. The integrated transformer arrangement further comprises a secondary inductor comprising a winding placed concentrically to a winding of the inductor loop, and the secondary inductor is configured to couple to the single-ended load.

Abstract: An ADC circuit (50) is disclosed. It comprises a global input configured to receive an input voltage (Vin) and a plurality of converter circuits (1051-105N). Each converter circuit (105j) comprises a comparator circuit (70j) having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit (70j). Furthermore, each converter circuit (105j) comprises a one-bit current-output DAC (110j) having an input directly controlled from the output of the comparator circuit (70j) and an output connected to the second input of the comparator circuit (70j). The second inputs of all comparator circuits are interconnected.

Abstract: A reference analog-to-digital converter (ADC) samples an input signal in parallel with sub-converters of a time-interleaved ADC. For each sub converter and for each of a plurality of output samples from the sub-converter, a calibration circuit determines whether the output sample from the sub-converter indicates an input signal polarity opposite that indicated by the reference ADC. For each such instance, a DC-offset sample is calculated as a difference between the output sample from the sub-converter and a target zero-crossing value for the sub-converter output. For each sub-converter, a series of DC-offset samples is filtered, to produce an average zero-crossing error for each sub-converter. This filtering may comprise a simple average, for example, or a moving average, a decaying filter, etc. Finally, a zero-crossing correction is applied for each of one or more of the sub-converters, based on the respective average zero-crossing error.

Abstract: A bias circuit for a PA. A first transistor has its drain terminal and its gate terminal connected to a first circuit node and its source terminal connected to a first supply terminal, a first current source connected to the first circuit node, and a first resistor connected between the first and second circuit nodes. A second transistor receives a first component of a differential input signal to the PA at its gate terminal, has its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal, and a third transistor receives a second component of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal. The gates terminals of the second and the third transistors are biased by a first voltage.

Abstract: A phase locked loop arrangement (1) beamforming comprises two or more phase locked loops. The loops include a phase comparator (21, 22) and an adjustable charge pump arrangement (31, 32) having a loop filter (51, 52) and charge pump current source (41, 42) with an adjustment input (?adj) connected to the loop filter (51, 52) to inject an adjustable charge pump current into the loop filter. A constant current source (71, 72) is configured to inject a first predetermined charge current into the loop filter (51, 52). The adjustable charge pump arrangements (31, 32) are connected to the respective phase comparators (21, 22) to provide a voltage control signal (vctrl) to an oscillator (61, 62) of the respective phase adjustable phase locked loop (11, 12) in response to the respective control signal (up, down) and to generate a phase deviation between the first and one of the at least one second oscillator signals (fosc1, fosc2) based on an adjustment signal applied to the adjustment input (?adj).

Abstract: A differential combiner circuit (200) comprises three ports each has two terminals (1a, 1b, 2a, 2b, 3a, 3b). The differential combiner circuit (200) further comprises a first sub-circuit comprising a first inductor (L1) connected between the first terminals (1a, 2a) of the first and second ports, and a first capacitor (C1) connected between the first terminals (2a, 3a) of the second and third ports; a second sub-circuit comprising a second inductor (L2) connected between the second terminals (1b, 2b) of the first and second ports, and a second capacitor (C2) connected between the second terminals (2b, 3b) of the second and third ports.

Abstract: A transmitter and method therein for transmitting a signal to a receiver in a wireless communication system are disclosed. The transmitter is configured to modulate a signal using two different modulations, a combination of binary amplitude shill keying, ASK, and binary frequency shift keying, FSK, and transmit the modulated signal.

Abstract: A limited-function, low-power wakeup receiver is based on frequency shift keying (FSK), avoiding the inherent problems of AM demodulation such as non-linearity of the amplitude detector. The FSK detector is easily realized in the digital domain. Due to the time discrete nature of FSK signals, the detector has a periodic response in frequency, allowing the signal to be demodulated at different offsets from the center frequency. The relaxed accuracy demands on the local oscillator frequency avoid the need for a power-hungry phase locked loop (PLL) circuit. To avoid potential loss if a signal coincides with one of the regular sensitivity nulls, the network at least occasionally transmits an FSK wakeup signal at a slightly shifted frequency, so at least one of the FSK wakeup signals will be received. Transmitting multiple frequency-shifted signals improves the likelihood of reception.

Abstract: The disclosure concerns controlling circuitry operably connectable to a plurality of constituent analog-to-digital converters (sub-ADCs) of an asynchronous time-interleaved analog-to-digital converter (TI-ADC). The controlling circuitry is configured to maintain a set of a number of sub-ADCs currently available for processing of an input sample, wherein the set is a subset of the plurality. Maintenance of the set is achieved by reception, from each of one or more of the sub-ADCs of the plurality, of an availability signal indicative of availability of the corresponding sub-ADC, and (responsive to the reception of the availability signal) addition of the corresponding sub-ADC to the set. Maintenance of the set is further achieved by (for each new input sample) selection of a sub-ADC of the set for processing of the new input sample, and (responsive to the selection) removal of the selected sub-ADC from the set and causing of the selected sub-ADC to process the new input sample.

Abstract: A wireless device features a low-power, limited-functionality, narrowband, homodyne wakeup receiver with a free running local oscillator. This enables a very attractive combination of low power consumption and high selectivity. The network supports these receivers by adopting a wakeup message structure that supports oscillator frequency calibration, and that tolerates loss of parts of the signal spectrum. Wakeup signals are transmitted frequently to allow the wakeup receivers (whether targeted by a wakeup signal or not) to calibrate their LO frequencies. The frequencies of the wakeup signals can be constant, or follow a hopping pattern for increased immunity to interference. The wakeup signals can use multiple carriers to increase robustness to loss of parts of the signal spectrum, particularly near the LO frequency in a homodyne receiver. The carriers use amplitude modulation (OOK), with either different or equal sequences.

Abstract: A signal generator with direct digital synthesis and tacking filter to generate an oscillator signal. A digital signal generator generates a digital signal; a digital to analog converter is connected to an output of the digital signal generator and converts the digital signal to an analog signal; a filter is coupled to an output of the DAC and filters the analog signal and generates the oscillator signal; a comparator is coupled to an output of the filter and generates a signal indicating zero crossings of the filter output signal; a digital control unit is coupled to outputs of the digital signal generator and comparator and generates a control signal to tune the filter to track a center frequency of the generated oscillator signal. The control signal is generated based on adjacent samples values from the digital signal generator before and after zero crossings of the filter output signal.