Abstract: An exemplary method and apparatus for MEMS device wafer level and/or array packaging comprises inter alia an EM shielding array of dielectric lid elements (340) sealed to a MEMS device die array (300) to produce a sealed MEMS device package array (330). Disclosed features and specifications may be variously controlled, adapted or otherwise optionally modified to improve hermetic sealing and/or EM shielding for any MEMS device. An exemplary embodiment of the present invention representatively provides for wafer level packaging of RF MEMS switches prior to device singulation.

Abstract: An exemplary method and apparatus for MEMS device control-chip integration and packaging comprises inter alia: a device substrate (300) comprising at least one MEMS device element (315) and at least a first interconnect pad (350); and a control-chip lid substrate (460) comprising at least a second interconnect pad (410), wherein the first interconnect pad (350) is suitably adapted for substantial engagement with the second interconnect pad (410) in order to communicably connect an integrated control chip (400) to a MEMS device element (315). Disclosed features and specifications may be variously controlled, adapted or otherwise optionally modified to improve component density and/or form factor for any MEMS device. An exemplary embodiment of the present invention representatively provides for HV control-chip driver integration and packaging of RF MEMS switches.

Abstract: An exemplary method and apparatus for MEMS device wafer level and/or array packaging comprises inter alia an EM shielding array of dielectric lid elements (340) sealed to a MEMS device die array (300) to produce a sealed MEMS device package array (330). Disclosed features and specifications may be variously controlled, adapted or otherwise optionally modified to improve hermetic sealing and/or EM shielding for any MEMS device. An exemplary embodiment of the present invention representatively provides for wafer level packaging of RF MEMS switches prior to device singulation.

Abstract: A component (10) includes a substrate (15), a cap wafer (23), and a protection layer (28) formed over a surface of the cap wafer (23). Together, the protection layer (28) and the cap wafer (23) form a cap structure (39) that is bonded to the substrate (15) via a bonding layer (33). An opening (47) is formed in the cap wafer (23) by etching the cap wafer (23). The protection layer (28) provides protection during etching of the cap wafer (23) for the underlying bonding layer (33) and devices (11,12) formed in the substrate (15).

Abstract: A component (10) includes a substrate (15), a cap wafer (23), and a protection layer (28) formed over a surface of the cap wafer (23). Together, the protection layer (28) and the cap wafer (23) form a cap structure (39) that is bonded to the substrate (15) via a bonding layer (33). An opening (47) is formed in the cap wafer (23) by etching the cap wafer (23). The protection layer (28) provides protection during etching of the cap wafer (23) for the underlying bonding layer (33) and devices (11,12) formed in the substrate (15).

Abstract: A semiconductor wafer level package used to encapsulate a device fabricated on a semiconductor substrate wafer before dicing of the wafer into individual chips. A cap wafer may be bonded to the semiconductor substrate using a low temperature frit glass layer as a bonding agent. The frit glass layer is in direct contact with the device. A hermetic seal is formed by a combination of the semiconductor substrate wafer, the cap wafer and the frit glass layer. A second embodiment of the package does not contain a cap wafer.

Abstract: A sensor (10) includes a cavity (31) formed by a substrate (11), an adhesive (21), and a filter (22). A sensing element (14) is located inside the cavity (31) while electrical contacts (17, 18) coupled to the sensing element (14) are located outside the cavity (31). The filter (22) protects the sensing element (14) from physical damage and contamination during die singulation and other assembly processes. The filter (22) also improves the chemical sensitivity, selectivity, response times, and refresh times of the sensing element (14).

Abstract: A spin-on dielectric for use in manufacturing semiconductors is produced. The dielectric is a siloxane polymer wherein each silicon atom is bonded to a polarization reducing group, and to three oxygen atoms each of which is bonded to one other silicon atom.

Abstract: A chemical sensor (10) is formed in part by depositing a stack of dielectric and resistive layers (13-15) on a support substrate (11). A cavity (17) is then formed on a substrate (16) to provide thermal isolation to the chemical sensor (10). The stack of dielectric and resistive layers (13-15) is then bonded to the substrate (16) and the support substrate (11) is removed. A layer of chemical sensing material (30) is then formed on the uppermost dielectric layer (15). Openings (33) may be formed through the stack of dielectric and resistive layers (13-15) to further enhance the thermal isolation of the chemical sensor (10) from the substrate (16).

Abstract: A method of operating chemical sensors (21) uses synchronously pulsed signals to reduce the power consumption of the chemical sensors (21). A first voltage source can be used to control and to heat multiple heating elements of the chemical sensors (21). The first voltage source can also be used to control other sensors which do not require elevated temperature operation. A second voltage source can be used to operate and bias the chemical sensors (21) heated by the multiple heating elements. Power consumption is reduced by turning or pulsing off the heating element (16) when it is not used.

Abstract: A process for forming different types of sensors, including metal oxide (10), calorimetric (44), and heterojunction (48), on the same semiconductor chip includes the steps of doping a top surface of a silicon substrate (16) with boron to form a diffusion region (18) for a resistive heater, forming a first silicon nitride layer (24) on the diffusion region, forming a first metal layer (26) on the first silicon nitride layer to provide a resistive temperature detector, forming a second silicon nitride layer (28) on the first metal layer, forming a second metal layer (34) on the second silicon nitride layer, and etching a sensing cavity (40) underneath and adjacent to the diffusion region using an anisotropic wet etchant and the diffusion region as an etch-stop. A metal oxide layer (36) is formed over the second metal layer for a metal oxide or heterojunction sensor. The sensor can optionally be suspended by tethers (38) within the sensing cavity.

Abstract: A sensor (10) includes a cavity (31) formed by a substrate (11), an adhesive (21), and a filter (22). A sensing element (14) is located inside the cavity (31) while electrical contacts (17, 18) coupled to the sensing element (14) are located outside the cavity (31). The filter (22) protects the sensing element (14) from physical damage and contamination during die singulation and other assembly processes. The filter (22) also improves the chemical sensitivity, selectivity, response times, and refresh times of the sensing element (14).

Abstract: A method for forming a semiconductor sensor FET device (2) comprises the steps of forming spaced-apart doped source (6) and drain (8) regions in a semiconductor substrate (4) with electrically conductive paths (16, 18) to each region. The region between the source (6) and drain (8) regions defines a gate region (12). An insulating layer (14, 15) is formed on the substrate (4) and source and drain regions (8), and a cantilever gate structure is formed using a sacrificial layer (60), such that a gate electrode (26) is supported on a cantilever support (28) and a cavity (22) separates the gate electrode (26) from the gate region (12). A conductive layer (34) is formed overlying the gate electrode (26) to provide a heater for the gate electrode (26). The chemical species collect in the cavity (22) and react with the surface (27) of the gate electrode (26).

Abstract: A semiconductor device having electronic circuitry formed in a semiconductor substrate (11) and separated from an overlying metal interconnect layer (18,18') using a fluorinated polymer dielectric (14,14') . The fluorinated polymer layer (14,14') may be formed directly on metallic surfaces, or formed on a semiconductor or non-metallic surface using an adhesion promoter (13,13'). Once formed, the fluorinated polymer layer (14,14') can be patterned to provide vias, and covered with a patterned metal interconnect layer (18,18') .

Abstract: An enclosure (8) for an electronic device (26) such as, for example, an accelerometer. The enclosure (8) includes a conductive semiconductor substrate (12) underlying the electronic device (26), a conductive cap (16) overlying the electronic device (26), and a power supply (25) having one or more outputs (27, 29) each with a substantially fixed potential wherein one output is electrically coupled to the conductive semiconductor substrate (12) and another output to the conductive cap (16). In a preferred embodiment, substrate ( 12 ) and cap (16) are coupled to the same power supply output (27). This coupling substantially eliminates the adverse effects of parasitic capacitances of the substrate (12) and cap (16) to reduce measurement error and EMI when a capacitive accelerometer is used as the electronic device (26).

Abstract: A method electrically and mechanically interconnects two surfaces of high density first and second semiconductor devices. The first semiconductor device (10) is formed with plug members (22) connected to nodes (18) of its circuit elements (14) and protruding from the first semiconductor device. The second semiconductor device (24) is formed having receptacle members (36) connected to nodes (32) of its circuit elements (28) and protruding from the second semiconductor device. The plug members are inserted into the receptacle member to interconnect the first and second semiconductor devices. The plug members may be removed from the receptacle member to disconnect the first and second semiconductor devices.

Abstract: A semicondutor device having electronic circuitry formed in a semiconductor substrate (11) and separated from an overlying metal interconnect layer (18, 18') using a fluorinated polymer dielectric (14,14'). The fluorinated polymer layer (14,14') may be formed directly on metallic surfaces, or formed on a semiconductor or non-metallic surface using an adhesion promoter (13,13'). Once formed, the fluorinated polymer layer (14,14') can be patterned to provide vias, and covered with a patterned metal interconnect layer (18, 18').

Abstract: A semiconductor wafer level package used to encapsulate a device fabricated on a semiconductor substrate wafer before dicing of the wafer into individual chips. A cap wafer is bonded to the semiconductor substrate wafer using a pre-patterned frit glass as a bonding agent such that the device is hermetically sealed inside a cavity. A hole in the cap wafer allows electrical connections to be made to the device through electrodes which pass through the frit glass seal.

Abstract: A method of fabricating a silicon film with improved thickness control and low defect density. The method comprises implanting a silicon wafer (19) with hydrogen ions to produce a layer of n-type silicon (18) having a precisely controlled thickness. Bonding the n-type silicon layer (18) to an oxidized surface (17) of a handle wafer (21) while using a temperature of 200 degrees Celsius. Etching the silicon wafer (19) to the boundary of the n-type layer (18). Annealing the silicon to drive out the hydrogen ions, leaving a silicon film (18) with a precisely controlled thickness and of the same type as the original silicon wafer (19).

Abstract: A method of anisotropically etching single crystal silicon includes providing single crystal silicon to be etched and placing it in an etching solution consisting essentially of R.sub.4 NOH and solvent wherein R is an alkyl group having between 0 and 4 carbon atoms. The solution will preferentially etch <100> or <110> oriented single crystal silicon. Additionally, electrochemical etching may be employed to preferentially etch P type single crystal silicon.