Patents by Inventor Henry Packard Moreton

Henry Packard Moreton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9058672
    Abstract: One embodiment of the present invention sets forth a technique controlling the pixel location at which the plane equation is evaluated. Multiple pixel offsets (dx, dy) may be specified that each define to a sub-pixel sample position. Attributes are then calculated for each sub-pixel sample position that is covered by a geometric primitive. One advantage of the technique is that anti-aliasing quality may be improved since high frequency color components may be selectively supersampled for particular geometric primitives.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: June 16, 2015
    Assignee: NVIDIA Corporation
    Inventors: John Erik Lindholm, Henry Packard Moreton, Ming Y. Siu, Stuart F. Oberman
  • Publication number: 20150109315
    Abstract: A system, method, and computer program product are provided for mapping tiles to physical memory locations. In use, a plurality of virtual tiles associated with a texture is identified. Additionally, a request to perform a mapping of the plurality of virtual tiles to one or more physical memory locations is received. Further, the plurality of virtual tiles is mapped to the one or more physical memory locations, utilizing a page table.
    Type: Application
    Filed: October 23, 2013
    Publication date: April 23, 2015
    Applicant: NVIDIA Corporation
    Inventors: Amanpreet Grewal, Andrei Khodakovsky, Yu Denny Dong, Henry Packard Moreton, Naveen Leekha
  • Publication number: 20150097847
    Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 9, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Jonathan DUNAISKY, Henry Packard MORETON, Jeffrey A. BOLZ, Yury Y. URALSKY, James Leroy DEMING, Rui M. BASTOS, Patrick R. BROWN, Amanpreet GREWAL, Christian AMSINCK, Poornachandra RAO, Jerome F. DULUK, JR., Andrew J. TAO
  • Publication number: 20150084952
    Abstract: A system, method, and computer program product are provided for processing a screen-aligned rectangle within a processing pipeline. The method includes the steps of determining coordinates for a screen-aligned rectangle by projecting a specification line onto a screen-space plane, computing a plane equation associated with the specification line, and rasterizing the screen-aligned rectangle that is within the screen-space plane based on the coordinates and the plane equation. The specification line is within a three-dimensional (3D) space. The plane equation is associated with a rendering parameter for the screen-aligned rectangle. The plane equation may be evaluated by a pixel shader in conjunction with processing the screen-aligned rectangle.
    Type: Application
    Filed: September 23, 2013
    Publication date: March 26, 2015
    Applicant: NVIDIA Corporation
    Inventor: Henry Packard Moreton
  • Publication number: 20150084974
    Abstract: One embodiment sets forth a method for allocating memory to surfaces. A software application specifies surface data, including interleaving state data. Based on the interleaving state data, a surface access unit bloats addressees derived from discrete coordinates associated with the surface, creating a bloated virtual address space with a predictable pattern of addresses that do not correspond to data. Advantageously, by creating predictable regions of addresses that do not correspond to data, the software application program may configure the surface to share physical memory space with one or more other surfaces. In particular, the software application may map the virtual address space together with one or more virtual address spaces corresponding to complementary data patterns to the same physical base address. And, by overlapping the virtual address spaces onto the same pages in physical address space, the physical memory may be more densely packed than by using prior-art allocation techniques.
    Type: Application
    Filed: September 20, 2013
    Publication date: March 26, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Eric B. LUM, Cass W. EVERITT, Henry Packard MORETON, Yury Y. URALSKY, Cyril CRASSIN, Jerome F. DULUK, Jr.
  • Publication number: 20150054827
    Abstract: A system, method, and computer program product are provided for passing attribute structures between shader stages of a processing pipeline. The method includes the steps of receiving data represented at a first level by a processing pipeline including an upstream shader unit, a downstream shader unit, and a processing unit. The upstream shader unit processes the data to generate a first set of attributes corresponding to the data represented at a second level. The upstream shader unit also stores the first set of the attributes in a first portion of a memory system that can be read by the downstream shader unit and any shader units that are downstream in the processing pipeline relative to the upstream shader unit. In one embodiment, the processing unit is coupled between the upstream shader unit and the downstream shader unit.
    Type: Application
    Filed: August 23, 2013
    Publication date: February 26, 2015
    Applicant: NVIDIA Corporation
    Inventors: Ziyad Sami Hakura, Henry Packard Moreton, Emmett M. Kilgariff
  • Publication number: 20150049104
    Abstract: One embodiment of the present invention includes techniques for processing a multi-resolution hierarchy, where an application configures a ROP unit to render all the levels included in the multi-resolution hierarchy to a single composite render target. The ROP unit renders memory pages to the composite render target in pitch order. In contrast, the texture unit accesses the composite render target with memory pages in pitch order for each level of the hierarchy. The application configures the MMU to ensure that the composite render target is correctly interpreted by the texture unit. Notably, the MMU translates ROP unit virtual addresses and texture unit virtual addresses using different mapping strategies to the same physical address space. One advantage of the disclosed embodiments is that rendering to the multi-resolution hierarchy does not require the CPU to execute the state parameter changes that are associated with rendering the different hierarchical levels using prior-art techniques.
    Type: Application
    Filed: August 16, 2013
    Publication date: February 19, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Eric B. LUM, Henry Packard MORETON
  • Publication number: 20140267356
    Abstract: A system, method, and computer program product are provided for multi-sample processing. The multi-sample pixel data is received and is analyzed to identify subsets of samples of a multi-sample pixel that have equal data, such that data for one sample in a subset represents multi-sample pixel data for all samples in the subset. An encoding state is generated that indicates which samples of the multi-sample pixel are included in each one of the subsets.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Alexander Lev Minkin, Henry Packard Moreton, Yury Uralsky, Eric Brian Lum, Dale L. Kirkland, Steven James Heinrich, Rui Manuel Bastos, Emmett M. Kilgariff, Jeffrey Alan Bolz, Tyson Bergland, Patrick R. Brown
  • Publication number: 20140267266
    Abstract: One embodiment of the present invention sets forth a technique for performing voxelization. The technique involves determining that a voxel is intersected by a first graphics primitive that has a front side and a back side and selecting one or more reference points within the voxel. The technique further involves, for each reference point, determining a distance from the reference point to the first graphics primitive and storing a first scalar value in an array based on the distance. The sign of the first scalar value reflects whether the reference point is located on the front side of the first graphics primitive or on the back side of the first graphics primitive.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Cyril CRASSIN, Yury Y. URALSKY, Eric ENDERTON, Eric B. LUM, Jerome F. DULUK, JR., Henry Packard MORETON, David LUEBKE
  • Publication number: 20140267260
    Abstract: A system, method, and computer program product are provided for executing processes involving at least one primitive in a graphics processor, utilizing a data structure. In operation, a data structure is associated with at least one primitive. Additionally, a plurality of processes involving the at least one primitive are executed in a graphics processor, utilizing the data structure. Moreover, the plurality of processes include at least one of selecting at least one surface or portion thereof to which to render, or selecting at least one of a plurality of viewports.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Ziyad Sami Hakura, Yury Uralsky, Tyson Bergland, Eric Brian Lum, Jerome F. Duluk, JR., Henry Packard Moreton
  • Publication number: 20140267264
    Abstract: One embodiment of the present invention sets forth a technique for performing voxelization. The technique involves identifying a voxel that is intersected by a first graphics primitive that has a front side and a back side and selecting a plurality of sample points within the voxel. The technique further involves determining, for each sample point included in the plurality of sample points, whether the sample point is located on the front side of the first graphics primitive or on the back side of the first graphics primitive. Finally, the technique involves storing, for at least a first sample point included in the plurality of sample points, a first result in a voxel mask reflecting whether the first sample point is located on the front side of the first graphics primitive or on the back side of the first graphics primitive.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Cyril CRASSIN, Yury Y. URALSKY, Eric ENDERTON, Eric B. LUM, Jerome F. DULUK, JR., Henry Packard MORETON, David LUEBKE
  • Publication number: 20140267224
    Abstract: Techniques are disclosed for storing post-z coverage data in a render target. A color raster operations (CROP) unit receives a coverage mask associated with a portion of a graphics primitive, where the graphics primitive intersects a pixel that includes a multiple samples, and the portion covers at least one sample. The CROP unit stores the coverage mask in a data field in the render target at a location associated with the pixel. One advantage of the disclosed techniques is that the GPU computes color and other pixel information only for visible fragments as determined by post-z coverage data. The GPU does not compute color and other pixel information for obscured fragments, thereby reducing overall power consumption and improving overall render performance.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Eric B. LUM, Rui Bastos, Jerome F. Duluk, JR., Henry Packard Moreton, Yury Y. Uralsky
  • Publication number: 20140267238
    Abstract: A system, method, and computer program product are provided for conservative rasterization of primitives using an error term. In use, an edge equation is determined for each edge of a primitive, the edge equation having coefficients defining the edge of the primitive. Each edge of the primitive is shifted to enlarge the primitive by modifying coefficients of the edge equation defining the edge by an error term that is a predetermined amount. Pixels that intersect the primitive are then determined using the enlarged primitive.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Eric Brian Lum, Walter Robert Steiner, Henry Packard Moreton, Justin L. Cobb, Barry Nolan Rodgers, Yury Uralsky, Timo Oskari Aila, Tero Tapani Karras
  • Publication number: 20140267265
    Abstract: One embodiment of the present invention sets forth a technique for performing voxelization. The technique involves determining that a first graphics primitive intersects a voxel and calculating a first set of coefficients associated with a first plane defined by the intersection of the first graphics primitive and the voxel. The technique further involves determining that a second graphics primitive intersects the voxel and calculating a second set of coefficients associated with a second plane defined by the intersection of the second graphics primitive and the voxel. The technique further involves calculating a third set of coefficients associated with a third surface based on the first set of coefficients and the second set of coefficients. The technique further involves calculating at least one of an amount of the voxel that is located on the back side of the third surface and an occlusion value based on the third set of coefficients.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Cyril CRASSIN, Yury Y. URALSKY, Eric ENDERTON, Eric B. LUM, Jerome F. DULUK, JR., Henry Packard MORETON, David LUEBKE
  • Publication number: 20140267366
    Abstract: A graphics processing pipeline within a parallel processing unit (PPU) is configured to perform path rendering by generating a collection of graphics primitives that represent each path to be rendered. The graphics processing pipeline determines the coverage of each primitive at a number of stencil sample locations within each different pixel. Then, the graphics processing pipeline reduces the number of stencil samples down to a smaller number of color samples, for each pixel. The graphics processing pipeline is configured to modulate a given color sample associated with a given pixel based on the color values of any graphics primitives that cover the stencil samples from which the color sample was reduced. The final color of the pixel is determined by downsampling the color samples associated with the pixel.
    Type: Application
    Filed: September 5, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Jeffrey A. BOLZ, Mark J. KILGARD, Henry Packard MORETON, Rui M. BASTOS, Eric B. LUM
  • Publication number: 20140267315
    Abstract: A system, method, and computer program product are provided for multi-sample processing. The multi-sample pixel data is received and an encoding state associated with the multi-sample pixel data is determined. Data for one sample of a multi-sample pixel and the encoding state are provided to a processing unit. The one sample of the multi-sample pixel is processed by the processing unit to generate processed data for the one sample that represents processed multi-sample pixel data for all samples of the multi-sample pixel or two or more samples of the multi-sample pixel.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Alexander Lev Minkin, Henry Packard Moreton, Yury Uralsky, Eric Brian Lum, Dale L. Kirkland, Steven James Heinrich, Rui Manuel Bastos, Emmett M. Kilgariff, Jeffrey Alan Bolz, Tyson Bergland, Patrick R. Brown
  • Publication number: 20140267276
    Abstract: A system, method, and computer program product are provided for generating primitive-specific attributes. In operation, it is determined whether a portion of a graphics processor is operating in a predetermined mode. If it is determined that the portion of the graphics processor is operating in the predetermined mode, only one or more primitive-specific attributes are generated in association with a primitive.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Ziyad Sami Hakura, Yury Uralsky, Tyson Bergland, Dale L. Kirkland, Cyril Jean-Francois Crassin, Henry Packard Moreton
  • Publication number: 20140267232
    Abstract: A system, method, and computer program product are provided for adjusting vertex positions. One or more viewport dimensions are received and a snap spacing is determined based on the one or more viewport dimensions. The vertex positions are adjusted to a grid according to the snap spacing. The precision of the vertex adjustment may increase as at least one dimension of the viewport decreases. The precision of the vertex adjustment may decrease as at least one dimension of the viewport increases.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Eric Brian Lum, Henry Packard Moreton, Kyle Perry Roden, Walter Robert Steiner, Ziyad Sami Hakura
  • Publication number: 20140253555
    Abstract: A technique for multiresolution consistent rasterization in which a setup unit calculates universal edge equations for a universal resolution. A rasterizer evaluates coverage data for two different resolutions based on the edge equations. The rasterizer evaluates coverage data for different effective pixel sizes—a large pixel size and a small pixel size. Optionally, the rasterizer may determine a first set of coverage data by performing conservative rasterization to determine coverage data for large pixels. Optionally, the rasterizer may then determine a second set of coverage data by performing standard rasterization for small pixels. Optionally, for the second set of coverage data, the rasterizer may evaluate only the small pixels that are within large pixels in the first set of coverage data that evaluate as covered.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Eric B. LUM, John S. MONTRYM, Walter R. STEINER, Justin COBB, Henry Packard MORETON
  • Patent number: 8773439
    Abstract: One embodiment of the present invention sets forth a technique for subdividing stroked higher-order curved segments into quadratic Bèzier curve segments. Path stroking may be accelerated when a GPU or other processor is configured to perform the subdivision operations. Cubic Bèzier path segments are subdivided into quadratic Bèzier curve segments and other lower-order segments at key features. The quadratic Bèzier curve segments approximate the cubic Bèzier path segments. A variance metric is computed for each quadratic Bèzier curve segment, and when the variance metric indicates that the quadratic Bèzier curve segment deviates by more than a threshold from the corresponding portion of the cubic Bèzier path segment, the quadratic Bèzier curve segment is further subdivided. The path composed of the quadratic Bèzier curve segments is then stroked by rendering hull geometry that encloses the path.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: July 8, 2014
    Assignee: NVIDIA Corporation
    Inventors: Mark J. Kilgard, Henry Packard Moreton