Patents by Inventor Heon-jong Shin

Heon-jong Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11876019
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: January 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Kim, Sunhom Steve Paak, Heon-Jong Shin, Dong-Ho Cha
  • Publication number: 20230403839
    Abstract: A semiconductor device comprises a first gate structure extending in a first direction and including a first gate electrode and a first gate capping pattern, a second gate structure spaced apart from the first gate structure and extending in the first direction, and including a second gate electrode and a second gate capping pattern, an active pattern extending in a second direction, the active pattern below the second gate structure, an epitaxial pattern on one side of the second gate structure and on the active pattern, a gate contact connected to the first gate electrode, and a node contact connected to the second gate electrode and to the epitaxial pattern. An upper surface of the gate contact is at a same level as the first gate capping pattern, and an upper surface of the node contact is lower than the upper surface of the first gate capping pattern.
    Type: Application
    Filed: August 25, 2023
    Publication date: December 14, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung Hun JUNG, Heon Jong SHIN, Min Chan GWAK, Sung Moon LEE, Jeong Ki HWANG
  • Patent number: 11778801
    Abstract: A semiconductor device comprises a first gate structure extending in a first direction and including a first gate electrode and a first gate capping pattern, a second gate structure spaced apart from the first gate structure and extending in the first direction, and including a second gate electrode and a second gate capping pattern, an active pattern extending in a second direction, the active pattern below the second gate structure, an epitaxial pattern on one side of the second gate structure and on the active pattern, a gate contact connected to the first gate electrode, and a node contact connected to the second gate electrode and to the epitaxial pattern. An upper surface of the gate contact is at a same level as the first gate capping pattern, and an upper surface of the node contact is lower than the upper surface of the first gate capping pattern.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: October 3, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Hun Jung, Heon Jong Shin, Min Chan Gwak, Sung Moon Lee, Jeong Ki Hwang
  • Patent number: 11769769
    Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: September 26, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwi-Chan Jun, Heon-jong Shin, In-chan Hwang, Jae-ran Jang
  • Patent number: 11721581
    Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: August 8, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Chan Gwak, Hwi Chan Jun, Heon Jong Shin, So Ra You, Sang Hyun Lee, In Chan Hwang
  • Publication number: 20230207654
    Abstract: A semiconductor device includes an active pattern that extends in a first direction; a plurality of gate structures that are spaced apart in the first direction, and include a gate electrode that extends in a second direction; a source/drain recess between adjacent gate structures; a source/drain pattern in the source/drain recess; a source/drain contact connected to the source/drain pattern and that includes a lower part on the source/drain pattern and an upper par; and a contact silicide film disposed along the lower part of the source/drain contact and between the source/drain contact and the source/drain region. The source/drain pattern includes a semiconductor liner film that extends along the source/drain recess and includes silicon germanium, a semiconductor filling film on the semiconductor liner film and that includes silicon germanium, and a semiconductor insertion film that extends along side walls of the lower part of the source/drain contact and includes silicon germanium.
    Type: Application
    Filed: November 11, 2022
    Publication date: June 29, 2023
    Inventors: DOO HYUN LEE, Heon Jong Shin, Hyun Ho Park, Seon-Bae Kim, Jin Young Park, Jae Ran Jang
  • Publication number: 20220301939
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Application
    Filed: June 2, 2022
    Publication date: September 22, 2022
    Inventors: Sung-Min KIM, Sunhom Steve PAAK, Heon-Jong SHIN, Dong-Ho CHA
  • Publication number: 20220208966
    Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.
    Type: Application
    Filed: March 21, 2022
    Publication date: June 30, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwi-Chan JUN, Heon-jong Shin, In-Chan Hwang, Jae-ran Jang
  • Patent number: 11316010
    Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gale line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwi-Chan Jun, Heon-jong Shin, In-chan Hwang, Jae-ran Jang
  • Publication number: 20220102491
    Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gale line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.
    Type: Application
    Filed: September 30, 2020
    Publication date: March 31, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwi-Chan JUN, Heon-jong SHIN, In-chan HWANG, Jae-ran JANG
  • Publication number: 20220068718
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Application
    Filed: November 10, 2021
    Publication date: March 3, 2022
    Inventors: Sung-Min KIM, Sunhom Steve PAAK, Heon-Jong SHIN, Dong-Ho CHA
  • Publication number: 20220020753
    Abstract: A semiconductor device comprises a first gate structure extending in a first direction and including a first gate electrode and a first gate capping pattern, a second gate structure spaced apart from the first gate structure and extending in the first direction, and including a second gate electrode and a second gate capping pattern, an active pattern extending in a second direction, the active pattern below the second gate structure, an epitaxial pattern on one side of the second gate structure and on the active pattern, a gate contact connected to the first gate electrode, and a node contact connected to the second gate electrode and to the epitaxial pattern. An upper surface of the gate contact is at a same level as the first gate capping pattern, and an upper surface of the node contact is lower than the upper surface of the first gate capping pattern.
    Type: Application
    Filed: February 25, 2021
    Publication date: January 20, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung Hun JUNG, Heon Jong SHIN, Min Chan GWAK, Sung Moon LEE, Jeong Ki HWANG
  • Patent number: 11201086
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: December 14, 2021
    Inventors: Sung-Min Kim, Sunhom Steve Paak, Heon-Jong Shin, Dong-Ho Cha
  • Publication number: 20210020509
    Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 21, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Chan GWAK, Hwi Chan JUN, Heon Jong SHIN, So Ra YOU, Sang Hyun LEE, In Chan HWANG
  • Patent number: 10879239
    Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gale line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: December 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwi-Chan Jun, Heon-jong Shin, In-chan Hwang, Jae-ran Jang
  • Publication number: 20200350312
    Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gale line. An insulating cover extends parallel to the substrate with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.
    Type: Application
    Filed: July 22, 2020
    Publication date: November 5, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwi-Chan Jun, Heon-jong Shin, In-chan Hwang, Jae-ran Jang
  • Patent number: 10818549
    Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: October 27, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Chan Gwak, Hwi Chan Jun, Heon Jong Shin, So Ra You, Sang Hyun Lee, In Chan Hwang
  • Patent number: 10763256
    Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: September 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwi-chan Jun, Heon-jong Shin, In-chan Hwang, Jae-ran Jang
  • Publication number: 20200235096
    Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.
    Type: Application
    Filed: April 3, 2020
    Publication date: July 23, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwi-chan JUN, Heon-jong SHIN, In-chan HWANG, Jae-ran JANG
  • Publication number: 20200227321
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Inventors: Sung-Min KIM, Sunhom Steve PAAK, Heon-Jong SHIN, Dong-Ho CHA