Patents by Inventor Heon-jong Shin
Heon-jong Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11876019Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.Type: GrantFiled: November 10, 2021Date of Patent: January 16, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Kim, Sunhom Steve Paak, Heon-Jong Shin, Dong-Ho Cha
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Publication number: 20230403839Abstract: A semiconductor device comprises a first gate structure extending in a first direction and including a first gate electrode and a first gate capping pattern, a second gate structure spaced apart from the first gate structure and extending in the first direction, and including a second gate electrode and a second gate capping pattern, an active pattern extending in a second direction, the active pattern below the second gate structure, an epitaxial pattern on one side of the second gate structure and on the active pattern, a gate contact connected to the first gate electrode, and a node contact connected to the second gate electrode and to the epitaxial pattern. An upper surface of the gate contact is at a same level as the first gate capping pattern, and an upper surface of the node contact is lower than the upper surface of the first gate capping pattern.Type: ApplicationFiled: August 25, 2023Publication date: December 14, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Sung Hun JUNG, Heon Jong SHIN, Min Chan GWAK, Sung Moon LEE, Jeong Ki HWANG
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Patent number: 11778801Abstract: A semiconductor device comprises a first gate structure extending in a first direction and including a first gate electrode and a first gate capping pattern, a second gate structure spaced apart from the first gate structure and extending in the first direction, and including a second gate electrode and a second gate capping pattern, an active pattern extending in a second direction, the active pattern below the second gate structure, an epitaxial pattern on one side of the second gate structure and on the active pattern, a gate contact connected to the first gate electrode, and a node contact connected to the second gate electrode and to the epitaxial pattern. An upper surface of the gate contact is at a same level as the first gate capping pattern, and an upper surface of the node contact is lower than the upper surface of the first gate capping pattern.Type: GrantFiled: February 25, 2021Date of Patent: October 3, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Hun Jung, Heon Jong Shin, Min Chan Gwak, Sung Moon Lee, Jeong Ki Hwang
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Patent number: 11769769Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.Type: GrantFiled: March 21, 2022Date of Patent: September 26, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hwi-Chan Jun, Heon-jong Shin, In-chan Hwang, Jae-ran Jang
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Patent number: 11721581Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.Type: GrantFiled: September 24, 2020Date of Patent: August 8, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Chan Gwak, Hwi Chan Jun, Heon Jong Shin, So Ra You, Sang Hyun Lee, In Chan Hwang
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Publication number: 20230207654Abstract: A semiconductor device includes an active pattern that extends in a first direction; a plurality of gate structures that are spaced apart in the first direction, and include a gate electrode that extends in a second direction; a source/drain recess between adjacent gate structures; a source/drain pattern in the source/drain recess; a source/drain contact connected to the source/drain pattern and that includes a lower part on the source/drain pattern and an upper par; and a contact silicide film disposed along the lower part of the source/drain contact and between the source/drain contact and the source/drain region. The source/drain pattern includes a semiconductor liner film that extends along the source/drain recess and includes silicon germanium, a semiconductor filling film on the semiconductor liner film and that includes silicon germanium, and a semiconductor insertion film that extends along side walls of the lower part of the source/drain contact and includes silicon germanium.Type: ApplicationFiled: November 11, 2022Publication date: June 29, 2023Inventors: DOO HYUN LEE, Heon Jong Shin, Hyun Ho Park, Seon-Bae Kim, Jin Young Park, Jae Ran Jang
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Publication number: 20220301939Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.Type: ApplicationFiled: June 2, 2022Publication date: September 22, 2022Inventors: Sung-Min KIM, Sunhom Steve PAAK, Heon-Jong SHIN, Dong-Ho CHA
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Publication number: 20220208966Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.Type: ApplicationFiled: March 21, 2022Publication date: June 30, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hwi-Chan JUN, Heon-jong Shin, In-Chan Hwang, Jae-ran Jang
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Patent number: 11316010Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gale line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.Type: GrantFiled: September 30, 2020Date of Patent: April 26, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hwi-Chan Jun, Heon-jong Shin, In-chan Hwang, Jae-ran Jang
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Publication number: 20220102491Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gale line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.Type: ApplicationFiled: September 30, 2020Publication date: March 31, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hwi-Chan JUN, Heon-jong SHIN, In-chan HWANG, Jae-ran JANG
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Publication number: 20220068718Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.Type: ApplicationFiled: November 10, 2021Publication date: March 3, 2022Inventors: Sung-Min KIM, Sunhom Steve PAAK, Heon-Jong SHIN, Dong-Ho CHA
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Publication number: 20220020753Abstract: A semiconductor device comprises a first gate structure extending in a first direction and including a first gate electrode and a first gate capping pattern, a second gate structure spaced apart from the first gate structure and extending in the first direction, and including a second gate electrode and a second gate capping pattern, an active pattern extending in a second direction, the active pattern below the second gate structure, an epitaxial pattern on one side of the second gate structure and on the active pattern, a gate contact connected to the first gate electrode, and a node contact connected to the second gate electrode and to the epitaxial pattern. An upper surface of the gate contact is at a same level as the first gate capping pattern, and an upper surface of the node contact is lower than the upper surface of the first gate capping pattern.Type: ApplicationFiled: February 25, 2021Publication date: January 20, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Sung Hun JUNG, Heon Jong SHIN, Min Chan GWAK, Sung Moon LEE, Jeong Ki HWANG
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Patent number: 11201086Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.Type: GrantFiled: March 30, 2020Date of Patent: December 14, 2021Inventors: Sung-Min Kim, Sunhom Steve Paak, Heon-Jong Shin, Dong-Ho Cha
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Publication number: 20210020509Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.Type: ApplicationFiled: September 24, 2020Publication date: January 21, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Chan GWAK, Hwi Chan JUN, Heon Jong SHIN, So Ra YOU, Sang Hyun LEE, In Chan HWANG
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Patent number: 10879239Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gale line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.Type: GrantFiled: July 22, 2020Date of Patent: December 29, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hwi-Chan Jun, Heon-jong Shin, In-chan Hwang, Jae-ran Jang
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Publication number: 20200350312Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gale line. An insulating cover extends parallel to the substrate with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.Type: ApplicationFiled: July 22, 2020Publication date: November 5, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hwi-Chan Jun, Heon-jong Shin, In-chan Hwang, Jae-ran Jang
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Patent number: 10818549Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.Type: GrantFiled: December 23, 2019Date of Patent: October 27, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Chan Gwak, Hwi Chan Jun, Heon Jong Shin, So Ra You, Sang Hyun Lee, In Chan Hwang
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Patent number: 10763256Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.Type: GrantFiled: April 3, 2020Date of Patent: September 1, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hwi-chan Jun, Heon-jong Shin, In-chan Hwang, Jae-ran Jang
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Publication number: 20200235096Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.Type: ApplicationFiled: April 3, 2020Publication date: July 23, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hwi-chan JUN, Heon-jong SHIN, In-chan HWANG, Jae-ran JANG
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Publication number: 20200227321Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.Type: ApplicationFiled: March 30, 2020Publication date: July 16, 2020Inventors: Sung-Min KIM, Sunhom Steve PAAK, Heon-Jong SHIN, Dong-Ho CHA