Abstract: This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.

Abstract: A vacuum processor includes a first transfer vessel that is connected on the back of a lock chamber connected on the back of an atmospheric transfer vessel and has a first robot; a second transfer vessel that is arranged at the back of this first transfer vessel, connected to the first transfer vessel, and has a second robot; a repeating vessel that connects the transfer vessels, and has a storage section in which the wafer is transferred between the robots; and a processing vessel that is connected, on an almost perpendicular side, to the repeating vessel around the second transfer vessel and in which the wafer is processed at a processing chamber, wherein the first robot has two arms that are expanded and contracted to both directions across a pivot axis, and the second robot has two arms that are expanded and contracted to the same direction around the pivot axis.

Abstract: A vacuum processing apparatus includes a first lock chamber and a second lock chamber coupled to a back face side of the atmospheric transfer chamber in parallel, a first transfer chamber coupled to a rear side of the first lock chamber, a second transfer chamber coupled, on the rear side of the first transfer chamber, a third transfer chamber coupled to the rear side of the second lock chamber, a first and a second relay chamber disposed between the first transfer chamber/the second transfer chamber and the first transfer chamber/the third transfer chamber to transfer a wafer between these chambers, and a plurality of processing chambers coupled to either the first, the second or the third transfer chamber, in addition, the number of the processing chambers coupled to the second transfer chamber is greater than that of the processing chambers coupled to either the first or the third transfer chamber, and the wafer alone processed in the processing chamber coupled to either the first or the second transfer ch

Abstract: This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.

Abstract: The apparatus includes a load lock adapted to store the workpiece inside and to be switched between atmosphere and vacuum; vacuum transport chambers connected to the load lock and to the corresponding process chambers in a state where the load lock and each of the process chambers are isolated mutually; transfer means for transferring the workpiece between each of the process chambers and the load lock via the corresponding vacuum transport chamber; load lock valves adapted to switch between interrupt and opening at a position between the load lock and the corresponding vacuum transport chambers; process chamber valves adapted to switch between interrupt and opening at a position between the process chambers and the corresponding vacuum transport chambers; and control means for controlling timing of the opening and closing of the valves whose timings are controlled in synchronization with the transfer of the workpieces.

Abstract: This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.

Abstract: The present invention provides an efficient transferring control method in a vacuum processing apparatus of a linear tool in which plural vacuum robots are arranged in transferring mechanical units to which process chambers are connected and processing-target members are passed and received among the plural vacuum robots. In addition, the present invention provides a vacuum processing apparatus in which there are provided plural controlling methods, and a unit which determines whether rates of the transferring robots are to be controlled or rates of the process chambers are to be controlled on the basis of processing time of each processing-target member and switches the controlling method in accordance with a site whose rate is controlled.

Abstract: Provided is a method for controlling efficient transferring operations in a vacuum processing apparatus with a linear tool. In the apparatus, plural transferring robots are arranged in transferring mechanism units in which plural process chambers are connected with each other, and to-be-processed wafers are received and passed between plural transferring robots. As the transferring robots is far from the load lock, the number of transferring operations to the process chambers is set larger, the number of times of continuous transferring operations to the process chambers is set as small as possible, and an odd number of times of continuous transferring operations to buffer rooms is set, by a destination determination unit and operation control rules. Further, transferring operations are performed based on the destination determination unit and the operation control rules.

Abstract: In a processing system of a linear tool in which plural carrying robots are arranged in carrying mechanical units to which processing modules are coupled and a processing target is delivered and received between the plural carrying robots, in the case where there are plural carrying routes on which the processing target is carried, the present invention provides a technique for determining the carrying route on which the highest throughput can be obtained. In the processing system of a linear tool, in the case where there are plural carrying routes on which the processing target is carried, the throughputs of the respective carrying routes are compared to each other, and the carrying route is determined by a unit for selecting the carrying route with the highest throughput.

Abstract: The invention provides a vacuum processing system of a semiconductor processing substrate and a vacuum processing method using the same, comprising an atmospheric transfer chamber having a plurality of cassette stands, a lock chamber arranged on a rear side of the atmospheric transfer chamber, and a first vacuum transfer chamber connected to a rear side of the lock chamber, wherein the first vacuum transfer chamber does not have any vacuum processing chamber connected thereto and has transfer intermediate chambers connected thereto, and the transfer intermediate chambers have subsequent vacuum transfer chambers connected thereto, and wherein the wafers are transferred via the lock chamber to the first vacuum transfer chamber to be processed in each of the subsequent vacuum processing chambers, which are further transferred via any of the transfer intermediate chambers connected to the first vacuum transfer chamber to the subsequent vacuum transfer chambers, and the respective wafers transferred to the subsequ

Abstract: A vacuum processing system of a semiconductor processing substrate and a vacuum processing method using the same comprises an atmospheric transfer chamber having a plurality of cassette stands for transferring a wafer, a lock chamber for storing the wafer transferred from the atmospheric transfer chamber, a first vacuum transfer chamber to which the wafer from the lock chamber is transferred, a transfer intermediate chamber connected to the first vacuum transfer chamber, a second vacuum transfer chamber connected to the transfer intermediate chamber, at least one vacuum processing chamber connected to the first vacuum transfer chamber, and two or more vacuum processing chambers connected to a rear side of the second vacuum transfer chamber, wherein the number of vacuum processing chambers connected to the first vacuum transfer chamber is smaller than the number of vacuum processing chambers connected to the second vacuum transfer chamber, or the number of use of vacuum processing chambers connected to the fir

Abstract: This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.

Abstract: This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.

Abstract: A semiconductor integrated circuit device capable of suppressing variations in transistor characteristics due to the well proximity effect is provided. Standard cell rows are arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction. In the standard cell rows, positions of the N well and the P region in the vertical direction are switched every other row. Adjacent standard cell rows share the P region or the N well. A distance from a PMOS transistor located at an end of a standard cell row to an end of an N well is greater than or equal to a width of an N well shared by standard cell rows.

Abstract: A transmitting and receiving circuit includes a transmitting side amplifier circuit amplifying a transmission signal transmitted from an antenna, a receiving side amplifier circuit amplifying a reception signal received by the antenna and being electrically connected to the a transmitting side amplifier circuit, a first matching circuit matching the antenna and the transmitting side amplifier circuit, a second matching circuit matching the antenna and the receiving side amplifier circuit, a first current source circuit capable of controlling an operating state and setting a first connection point between the first matching circuit and an output terminal of the transmitting side amplifier circuit to a given voltage, and a second current source circuit capable of controlling an operating state and setting a second connection point between the second matching circuit and an input terminal of the receiving side amplifier circuit to a given voltage.

Abstract: A filter circuit includes a low-pass filter and a calibration circuit calibrating a frequency characteristic of the low-pass filter. The calibration circuit includes a negative feedback circuit and a control circuit.

Abstract: The invention provides a plasma treatment apparatus or a plasma treatment method having a high productivity while maintaining a stable treatment performance.

Abstract: A filter circuit includes a low-pass filter and a calibration circuit calibrating a frequency characteristic of the low-pass filter. The calibration circuit includes a negative feedback circuit and a control circuit.

Abstract: This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.

Abstract: A semiconductor integrated circuit device capable of suppressing variations in transistor characteristics due to the well proximity effect is provided. Standard cell rows are arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction. In the standard cell rows, positions of the N well and the P region in the vertical direction are switched every other row. Adjacent standard cell rows share the P region or the N well. A distance from a PMOS transistor located at an end of a standard cell row to an end of an N well is greater than or equal to a width of an N well shared by standard cell rows.