Patents by Inventor Hideaki Nakahara

Hideaki Nakahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6647522
    Abstract: A semiconductor device having multiple memory circuits of varying sizes includes scan test circuitry that enables the memories to be simultaneous loaded with pattern data and tested. A first memory circuit has a first memory, a first address scan chain that receives serial scan-in address data and generates a first address signal, and a first data scan chain that receives serial scan-in data and generates a first data input signal. A second memory circuit has a second memory, a second address scan chain that receives the serial scan-in address data and generates a second address signal, and a second data scan chain that receives the serial scan-in data and generates a second data input signal.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: November 11, 2003
    Assignee: Fujitsu Limited
    Inventors: Hideaki Nakahara, Masahiko Sudo, Yasuhiro Kawakami, Terumi Yoshimura, Kiminori Kato, Tetsuya Hiramatsu