Patents by Inventor Hideaki Shishido

Hideaki Shishido has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955612
    Abstract: A power storage system with excellent characteristics is provided. A power storage system with a high degree of safety is provided. A power storage system with less deterioration is provided. A storage battery with excellent characteristics is provided. The power storage system includes a neural network and a storage battery. The neural network includes an input layer, an output layer, and one or more hidden layers between the input layer and the output layer. The predetermined hidden layer is connected to the previous hidden layer or the previous input layer by a predetermined weight coefficient, and connected to the next hidden layer or the next output layer by a predetermined weight coefficient. In the storage battery, voltage and time at which the voltage is obtained are measured as one of sets of data. The sets of data measured at different times are input to the input layer and the operational condition of the storage battery is changed in accordance with a signal output from the output layer.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: April 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazutaka Kuriki, Ryota Tajima, Kouhei Toyotaka, Hideaki Shishido, Toshiyuki Isa
  • Publication number: 20240113130
    Abstract: A semiconductor device including a capacitor whose charge capacity is increased while improving the aperture ratio is provided. Further, a semiconductor device which consumes less power is provided. A transistor which includes a light-transmitting semiconductor film, a capacitor in which a dielectric film is provided between a pair of electrodes, an insulating film which is provided over the light-transmitting semiconductor film, and a first light-transmitting conductive film which is provided over the insulating film are included. The capacitor includes the first light-transmitting conductive film which serves as one electrode, the insulating film which functions as a dielectric, and a second light-transmitting conductive film which faces the first light-transmitting conductive film with the insulating film positioned therebetween and functions as the other electrode.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Shunpei YAMAZAKI, Hiroyuki MIYAKE, Hideaki SHISHIDO, Jun KOYAMA
  • Publication number: 20240105732
    Abstract: A novel display device or the like in which a transistor connected to a scan line has small gate capacitance is provided. A novel display device or the like in which a scan line has low resistance is provided. A novel display device or the like in which pixels can be arranged with high density is provided. A novel display device or the like that can be manufactured without an increase in cost is provided. In a transistor including a first gate electrode and a second gate electrode, the first gate electrode is formed using a metal material with low resistance and the second gate electrode is formed using a metal oxide material that can reduce oxygen vacancies in an oxide semiconductor layer. The first gate electrode is connected to the scan line, and the second gate electrode is connected to a wiring to which a constant potential is supplied.
    Type: Application
    Filed: October 11, 2023
    Publication date: March 28, 2024
    Inventors: Kouhei TOYOTAKA, Kei TAKAHASHI, Hideaki SHISHIDO, Koji KUSUNOKI
  • Publication number: 20240105737
    Abstract: Provided is a display device with extremely high resolution, a display device with higher display quality, a display device with improved viewing angle characteristics, or a flexible display device. Same-color subpixels are arranged in a zigzag pattern in a predetermined direction. In other words, when attention is paid to a subpixel, another two subpixels exhibiting the same color as the subpixel are preferably located upper right and lower right or upper left and lower left. Each pixel includes three subpixels arranged in an L shape. In addition, two pixels are combined so that pixel units including subpixel are arranged in matrix of 3×2.
    Type: Application
    Filed: December 11, 2023
    Publication date: March 28, 2024
    Inventors: Hisao IKEDA, Kouhei TOYOTAKA, Hideaki SHISHIDO, Hiroyuki MIYAKE, Kohei YOKOYAMA, Yasuhiro JINBO, Yoshitaka DOZEN, Takaaki NAGATA, Shinichi HIRASA
  • Patent number: 11942170
    Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiko Amano, Kouhei Toyotaka, Hiroyuki Miyake, Aya Miyazaki, Hideaki Shishido, Koji Kusunoki
  • Publication number: 20240094575
    Abstract: To provide a thin touch panel, a touch panel having a simple structure, a touch panel which can be easily incorporated into an electronic device, or a touch panel with a small number of components. The touch panel includes pixel electrodes arranged in a matrix, a plurality of signal lines, a plurality of scan lines, a plurality of first wirings extending in a direction parallel to the signal lines, and a plurality of second wirings extending in a direction parallel to the scan line. Part of the first wiring and part of the second wiring function as a pair of electrodes included in a touch sensor. The first wiring and the second wiring each have a stripe shape or form a mesh shape and are each provided between two adjacent pixel electrodes in a plan view.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventors: Hideaki SHISHIDO, Daisuke KUBOTA, Yusuke KUBOTA
  • Patent number: 11933974
    Abstract: An object is to provide an electronic device capable of recognizing a user's facial feature accurately. A glasses-type electronic device includes a first optical component, a second optical component, a frame, an imaging device, a feature extraction unit, and an emotion estimation unit. The frame is in contact with a side surface of the first optical component and a side surface of the second optical component. The imaging device is in contact with the frame and has a function of detecting part of a user's face. The feature extraction unit has a function of extracting a feature of the user's face from the detected part of the user's face. The emotion estimation unit has a function of estimating information on the user from the extracted feature.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: March 19, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takayuki Ikeda, Hidetomo Kobayashi, Hideaki Shishido, Kiyotaka Kimura, Takashi Nakagawa, Kosei Nei, Kentaro Hayashi
  • Publication number: 20240062724
    Abstract: A high-definition display device is provided. A small display device is provided. In the display device, a first layer and a second layer are stacked and provided. The first layer includes a gate driver circuit and a source driver circuit, and the second layer includes a display portion. The gate driver circuit and the source driver circuit are provided to include a region overlapping with the display portion. The gate driver circuit and the source driver circuit have an overlap region where they are not strictly separated from each other. Five or more gate driver circuits and five or more source driver circuits can be provided.
    Type: Application
    Filed: October 16, 2023
    Publication date: February 22, 2024
    Inventors: Takayuki IKEDA, Hidetomo KOBAYASHI, Hideaki SHISHIDO, Kiyotaka KIMURA, Takashi NAKAGAWA, Kosei NEI
  • Patent number: 11901485
    Abstract: An object is to provide a light-emitting display device in which a pixel including a thin film transistor using an oxide semiconductor has a high aperture ratio. The light-emitting display device includes a plurality of pixels each including a thin film transistor and a light-emitting element. The pixel is electrically connected to a first wiring functioning as a scan line. The thin film transistor includes an oxide semiconductor layer over the first wiring with a gate insulating film therebetween. The oxide semiconductor layer is extended beyond the edge of a region where the first wiring is provided. The light-emitting element and the oxide semiconductor layer overlap with each other.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: February 13, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryo Arasawa, Hideaki Shishido
  • Patent number: 11881489
    Abstract: Provided is a display device with extremely high resolution, a display device with higher display quality, a display device with improved viewing angle characteristics, or a flexible display device. Same-color subpixels are arranged in a zigzag pattern in a predetermined direction. In other words, when attention is paid to a subpixel, another two subpixels exhibiting the same color as the subpixel are preferably located upper right and lower right or upper left and lower left. Each pixel includes three subpixels arranged in an L shape. In addition, two pixels are combined so that pixel units including subpixel are arranged in matrix of 3×2.
    Type: Grant
    Filed: November 22, 2022
    Date of Patent: January 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisao Ikeda, Kouhei Toyotaka, Hideaki Shishido, Hiroyuki Miyake, Kohei Yokoyama, Yasuhiro Jinbo, Yoshitaka Dozen, Takaaki Nagata, Shinichi Hirasa
  • Patent number: 11870042
    Abstract: A sensor element with excellent characteristics is provided. An electronic device including a power storage system with excellent characteristics is provided. A vehicle including a power storage system with excellent characteristics is provided. A novel semiconductor device is provided. The power storage system includes a storage battery, a neural network, and a sensor element; the neural network includes an input layer, an output layer, and one or a plurality of middle layers provided between the input layer and the output layer; a value corresponding to a first signal output from the sensor element is supplied to the input layer; the first signal is an analog signal; the sensor element includes a region in contact with a surface of the storage battery; and the sensor element has a function of measuring one or both of strain and temperature.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: January 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mayumi Mikami, Ryota Tajima, Hideaki Shishido, Kensuke Yoshizumi
  • Patent number: 11842002
    Abstract: To provide an inexpensive display device. The display device includes a pixel and an IC chip. The pixel includes a first pixel circuit including a display element and a second pixel circuit including a light-receiving device. The one IC chip includes a control circuit, a data driver circuit, and a read circuit. The first and second pixel circuits are electrically connected to the read circuit. The control circuit has a function of controlling driving of the data driver circuit and the read circuit. The data driver circuit has a function of supplying image data to the first pixel circuit. The read circuit has a function of outputting a monitor signal corresponding to a monitor current when the monitor current flows through the first pixel circuit. The read circuit also has a function of outputting an imaging signal corresponding to imaging data acquired by the second pixel circuit.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: December 12, 2023
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kei Takahashi, Hidetomo Kobayashi, Hajime Kimura, Takeshi Osada, Hideaki Shishido, Kiyotaka Kimura, Shuichi Katsui, Takeya Hirose, Takayuki Ikeda
  • Publication number: 20230397444
    Abstract: An imaging device that has an image processing function and is capable of operating at high speed is provided. The imaging device has an additional function such as image processing, image data obtained by an imaging operation is binarized in a pixel portion, and a product-sum operation is performed using the binarized data. A memory circuit is provided in the pixel portion and retains a weight coefficient used for the product-sum operation. Thus, an arithmetic operation can be performed without the weight coefficient read from the outside every time, so that power consumption can be reduced. Furthermore, a pixel circuit, a memory circuit, and the like and a product-sum operation circuit and the like are formed to be stacked; therefore, the length of a wiring between the circuits can be shortened, and a low-power consumption operation and a high-speed operation can be performed.
    Type: Application
    Filed: September 9, 2021
    Publication date: December 7, 2023
    Inventors: Yusuke NEGORO, Hideaki SHISHIDO
  • Publication number: 20230396899
    Abstract: The present invention relates to a highly functional imaging device that can be manufactured through a small number of steps. The imaging device is formed in such a manner that a first stacked body in which a plurality of devices are stacked and a second stacked body in which a plurality of devices are stacked are bonded to each other. For example, a pixel circuit, a driver circuit of a pixel, and the like can be provided in the first stacked body, and a reading circuit of the pixel circuit, a memory circuit, a driver circuit of the memory circuit, and the like can be provided in the second stacked body. With these structures, the imaging device which is small can be formed. Furthermore, wiring delay or the like can be prevented by stacking circuits, so that high-speed operation can be performed.
    Type: Application
    Filed: September 13, 2021
    Publication date: December 7, 2023
    Inventors: Yusuke NEGORO, Hideaki SHISHIDO
  • Patent number: 11835809
    Abstract: To provide a thin touch panel, a touch panel having a simple structure, a touch panel which can be easily incorporated into an electronic device, or a touch panel with a small number of components. The touch panel includes pixel electrodes arranged in a matrix, a plurality of signal lines, a plurality of scan lines, a plurality of first wirings extending in a direction parallel to the signal lines, and a plurality of second wirings extending in a direction parallel to the scan line. Part of the first wiring and part of the second wiring function as a pair of electrodes included in a touch sensor. The first wiring and the second wiring each have a stripe shape or form a mesh shape and are each provided between two adjacent pixel electrodes in a plan view.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: December 5, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Shishido, Daisuke Kubota, Yusuke Kubota
  • Publication number: 20230386383
    Abstract: A display device with a narrower frame can be provided. In the display device, a first layer, a second layer, and a third layer are provided to be stacked. The first layer includes a gate driver circuit and a data driver circuit, the second layer includes a demultiplexer circuit, and the third layer includes a display portion. In the display portion, pixels are arranged in a matrix, an input terminal of the demultiplexer circuit is electrically connected to the data driver circuit, and an output terminal of the demultiplexer circuit is electrically connected to some of the pixels. The gate driver circuit and the data driver circuit are provided to include a region overlapping some of the pixels. The gate driver circuit and the data driver circuit have a region where they are not strictly separated from each other and overlap each other. Five or more gate driver circuits and five or more data driver circuits can be provided.
    Type: Application
    Filed: April 6, 2023
    Publication date: November 30, 2023
    Inventors: Takashi NAKAGAWA, Takayuki IKEDA, Hidetomo KOBAYASHI, Hideaki SHISHIDO, Shuichi KATSUI, Kiyotaka KIMURA
  • Publication number: 20230369344
    Abstract: A semiconductor device including a first transistor, a second transistor, and an insulating layer is provided. The first transistor includes a first semiconductor layer and a first conductive layer. The second transistor includes a second semiconductor layer and a second conductive layer. The insulating layer includes a first side surface over the first conductive layer and a second side surface over the second conductive layer. A gate insulating layer includes a portion facing the first side surface with the first semiconductor layer therebetween and a portion facing the second side surface with the second semiconductor layer therebetween. A gate electrode includes a portion facing the first side surface with the gate insulating layer and the first semiconductor layer therebetween and a portion facing the second side surface with the gate insulating layer and the second semiconductor layer therebetween. The first semiconductor layer is electrically connected to the second semiconductor layer.
    Type: Application
    Filed: April 28, 2023
    Publication date: November 16, 2023
    Inventors: Koji KUSUNOKI, Susumu KAWASHIMA, Hideaki SHISHIDO, Tomoaki ATSUMI, Motoharu SAITO
  • Patent number: 11798491
    Abstract: A high-definition display device is provided. A small display device is provided. In the display device, a first layer and a second layer are stacked and provided. The first layer includes a gate driver circuit and a source driver circuit, and the second layer includes a display portion. The gate driver circuit and the source driver circuit are provided to include a region overlapping with the display portion. The gate driver circuit and the source driver circuit have an overlap region where they are not strictly separated from each other. Five or more gate driver circuits and five or more source driver circuits can be provided.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: October 24, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Ikeda, Hidetomo Kobayashi, Hideaki Shishido, Kiyotaka Kimura, Takashi Nakagawa, Kosei Nei
  • Publication number: 20230335605
    Abstract: A novel semiconductor device is provided. The semiconductor device is a single-polarity semiconductor device including a vertical-channel transistor. In the vertical-channel transistor, the higher parasitic capacitance value of the gate-source parasitic capacitance and the gate-drain parasitic capacitance is used as a bootstrap capacitor, which decreases the occupied area of the semiconductor device. The use of an oxide semiconductor for a semiconductor layer of the vertical-channel transistor increases the breakdown voltage between the source and the drain, which can shorten the channel length. In addition, stable operation can be performed even in a high-temperature environment.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 19, 2023
    Inventors: Koji KUSUNOKI, Susumu KAWASHIMA, Hideaki SHISHIDO, Tomoaki ATSUMI, Motoharu SAITO
  • Patent number: 11791344
    Abstract: A novel display device or the like in which a transistor connected to a scan line has small gate capacitance is provided. A novel display device or the like in which a scan line has low resistance is provided. A novel display device or the like in which pixels can be arranged with high density is provided. A novel display device or the like that can be manufactured without an increase in cost is provided. In a transistor including a first gate electrode and a second gate electrode, the first gate electrode is formed using a metal material with low resistance and the second gate electrode is formed using a metal oxide material that can reduce oxygen vacancies in an oxide semiconductor layer. The first gate electrode is connected to the scan line, and the second gate electrode is connected to a wiring to which a constant potential is supplied.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: October 17, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kouhei Toyotaka, Kei Takahashi, Hideaki Shishido, Koji Kusunoki