Patents by Inventor Hideaki Uchida

Hideaki Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5637434
    Abstract: In a method for producing a toner for electrostatic development, a mixture of starting toner materials comprising at least a resin and a colorant is kneaded, extruded and cooled to obtain a toner material. The toner material is crushed and then pulverized by an impact pulverizer having a pulverizing section formed by disposing a stator having ridges of a triangular waveform at an inner surface thereof and a rotor having ridges of a triangular waveform at an outer surface thereof at a gap between the ridges of the stator and of the rotor.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: June 10, 1997
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Susumi Ikushima, Shingo Ishiyama, Sadaki Yagi, Hideaki Uchida
  • Patent number: 5619151
    Abstract: A semiconductor memory device which includes at least one of (1) an input buffer circuit which generates internal address signals in response to an incoming address; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; a
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 8, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Akioka, Masahiro Iwamura, Atsushi Hiraishi, Yuji Yokoyama, Nozomu Matsuzaki, Tatsumi Yamauchi, Yutaka Kobayashi, Nobuyuki Gotou, Akira ide, Masahiro Yamamura, Hideaki Uchida
  • Patent number: 5513091
    Abstract: A voltage transforming circuit comprises a constant-voltage regulator circuit for receiving a first voltage from a first voltage source and outputting a second voltage having the same polarity as the first voltage and a predetermined absolute value lower than the same, a step-up circuit, having a plurality of output terminals, for receiving the second voltage and a first synchronization signal, the step-up circuit stepping up the absolute value of the second voltage and controlling the operation of charging capacitors, thereby outputting from the output terminals a plurality of stepped-up voltages of the same polarity having absolute values higher than the second voltage, a level shifter circuit for receiving a second synchronization signal which uses the first voltage as one of logic levels, and receiving that one of the stepped-up voltages which has a highest absolute value higher than that of the first voltage, the level shifter circuit shifting the voltage of the one of logic levels to the highest absolut
    Type: Grant
    Filed: March 23, 1995
    Date of Patent: April 30, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Uchida, Kouji Oohashi
  • Patent number: 5502820
    Abstract: An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.
    Type: Grant
    Filed: February 8, 1995
    Date of Patent: March 26, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Hiraishi, Takashi Akioka, Yutaka Kobayashi, Yuji Yokoyama, Masahiro Iwamura, Tatsumi Yamauchi, Shigeru Takahashi, Hideaki Uchida, Akira Ide
  • Patent number: 5497023
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Grant
    Filed: December 8, 1994
    Date of Patent: March 5, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikasu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Patent number: 5398318
    Abstract: An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.
    Type: Grant
    Filed: November 2, 1990
    Date of Patent: March 14, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Hiraishi, Takashi Akioka, Yutaka Kobayashi, Yuji Yokoyama, Masahiro Iwamura, Tatsumi Yamauchi, Shigeru Takahashi, Hideaki Uchida, Akira Ide
  • Patent number: 5386135
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Grant
    Filed: April 12, 1994
    Date of Patent: January 31, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Patent number: 5371713
    Abstract: In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.
    Type: Grant
    Filed: March 9, 1994
    Date of Patent: December 6, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Katsumi Ogiue, Yukio Suzuki, Ikuro Masuda, Masanori Odaka, Hideaki Uchida
  • Patent number: 5345421
    Abstract: A wide-bit output semiconductor storage device of high speed and low noise is provided in which output circuits are grouped into two groups and the two output circuit groups are so controlled as to be switched in directions of levels which are opposite to each other.
    Type: Grant
    Filed: June 29, 1992
    Date of Patent: September 6, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Iwamura, Tatsumi Yamauchi, Makoto Saeki, Hideaki Uchida
  • Patent number: 5324982
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Grant
    Filed: October 2, 1991
    Date of Patent: June 28, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Patent number: 5311482
    Abstract: In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.
    Type: Grant
    Filed: July 16, 1993
    Date of Patent: May 10, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Katsumi Ogiue, Yukio Suzuki, Ikuro Masuda, Masanori Odaka, Hideaki Uchida
  • Patent number: 5241506
    Abstract: A random access memory (RAM) array has a dummy word line having a similar pattern to the word lines provided for the RAM cells. A transistor having the same channel width and channel length as one of the transistors in the RAM cells has its gate connected to the dummy word line. An inverter is formed of three transistors including the transistor having its gate connected to the dummy word line, with the output of the inverter connected to a capacitor. The capacitance of the capacitor is set close to the capacitance of a bus line of the RAM to adjust the dummy word line and the word lines of the RAM circuits to have the same transfer delay. If the capacitance of the capacitor is made slightly smaller than the bus line capacitance, the potential at the output of the inverter can be changed by this difference. The output of the inverter is detected, and can be used as a drive signal to drive a sense amplifier used to read the RAM cells.
    Type: Grant
    Filed: November 14, 1990
    Date of Patent: August 31, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Motegi, Hideaki Uchida, Yasunori Kuwashima
  • Patent number: 5168100
    Abstract: Disclosed are novel HP530 compounds, their derivatives or their pharmaceutically permissible salts, a process for preparing them and an antitumor substances containing them as active ingredient. The HP530 compounds and their derivatives expressed by the general formula below can be prepared by cultivating Streptomyces sp. HP530 (FERM BP-2786) or and chemically derivation. ##STR1## where X is a C.sub.2 -C.sub.4 acyl group or a hydrogen atom, Y is a C.sub.2 -C.sub.4 acyl group or a hydrogen atom and Z is a group expressed by the formula (II), (III) or (IV).
    Type: Grant
    Filed: March 12, 1991
    Date of Patent: December 1, 1992
    Assignee: Sapporo Breweries Limited
    Inventors: Naoki Abe, Nobuyasu Enoki, Yasukazu Nakakita, Hideaki Uchida, Ryoichi Sato, Suguru Takeo, Nobuhiro Watanabe
  • Patent number: 5148255
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Grant
    Filed: January 23, 1991
    Date of Patent: September 15, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Patent number: 5091883
    Abstract: An input buffer for processing an external signal is provided in one of passways, which is the most closest to a line for equally dividing the whole of a plurality of memory cell blocks longitudinally or laterally into two sections, the passway interposing between the adjacent memory cell blocks of the plurality of memory cell blocks to which a processed signal of the input buffer is transmitted, whereby the length of the signal pass from the input buffer to each memory cell of the memory cell blocks can be shortened. Therefore, since the memory cell or a logic element existing between the input buffer and the memory cell is operated by a pulse of little distortion without delay of time, a access time can be reduced and a processing speed of a microprocessor can be increased. Further, a degree of freedom in designing a system of a memory or the microprocessor is further improved.
    Type: Grant
    Filed: July 13, 1990
    Date of Patent: February 25, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Nozomu Matsuzaki, Takashi Akioka, Masahiro Iwamura, Atushi Hiraishi, Tatsumi Yamauchi, Yuji Yokoyama, Yutaka Kobayashi, Hideaki Uchida
  • Patent number: 5059838
    Abstract: A delay circuit delays an input signal having a predetermined frequency by a time corresponding to a control signal. A delay amount detector detects a signal delay amount of the delay circuit. A charge pump circuit generates a DC voltage corresponding to a pulse width ratio between the input signal and a detection signal of the delay amount detector. This DC voltage is fed back to the delay circuit as a control signal.
    Type: Grant
    Filed: January 17, 1990
    Date of Patent: October 22, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Motegi, Kenji Matsuo, Akira Nagae, Hideaki Uchida
  • Patent number: 5050127
    Abstract: A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.
    Type: Grant
    Filed: October 19, 1989
    Date of Patent: September 17, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Kinya Mitsumoto, Shinji Nakazato, Yoshiaki Yazawa, Masanori Odaka, Hideaki Uchida, Nobuaki Miyakawa
  • Patent number: 5042010
    Abstract: In order to provide high speed and lower power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portiosn of the circuit use CMOS elements of lower power consumption. This arrangement is particulary advantageous in memory circuits.
    Type: Grant
    Filed: May 8, 1990
    Date of Patent: August 20, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Katsumi Ogiue, Yukio Suzuki, Ikuro Masuda, Masanori Odaka, Hideaki Uchida
  • Patent number: 5029323
    Abstract: A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.
    Type: Grant
    Filed: August 29, 1989
    Date of Patent: July 2, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Nakazato, Hideaki Uchida, Nobuo Tanba, Nobuyuki Gotoo, Kazunori Onozawa, Atsushi Hiraishi
  • Patent number: 4924439
    Abstract: In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.
    Type: Grant
    Filed: May 30, 1989
    Date of Patent: May 8, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Katsumi Ogiue, Yukio Suzuki, Ikuro Masuda, Masanori Odaka, Hideaki Uchida