Patents by Inventor Hidefumi Rikimaru

Hidefumi Rikimaru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240256037
    Abstract: To provide a novel electronic device. The electronic device includes a housing and a display device. The display device includes a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are provided in different layers. The first layer includes a driver circuit and an arithmetic circuit. The second layer includes pixel circuits and a cell array. The third layer includes light-receiving devices and light-emitting devices. The pixel circuits each have a function of controlling light emission of the light-emitting device. The driver circuit has a function of controlling the pixel circuits. The arithmetic circuit has a function of performing arithmetic processing on the basis of first data corresponding to currents output from the light-receiving devices and second data corresponding to a potential held in the cell array.
    Type: Application
    Filed: March 4, 2024
    Publication date: August 1, 2024
    Inventors: Yoshiyuki KUROKAWA, Hiromichi GODO, Kouhei TOYOTAKA, Kazuki TSUDA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Publication number: 20240234310
    Abstract: A novel semiconductor device is provided. In reservoir computing using an input layer, a reservoir layer, and an output layer, variation in threshold voltage between transistors is used as a weight used for product arithmetic processing. Two transistors are provided in one product arithmetic circuit and data u is supplied to gates of the two transistors. Drain current of each of the transistors is determined by the data u and the threshold voltage of the transistor. The difference between the drain currents corresponds to a product arithmetic result. The difference between the drain currents is converted into voltage to be output. A plurality of product arithmetic circuits are connected in parallel to form a product-sum arithmetic circuit.
    Type: Application
    Filed: May 13, 2022
    Publication date: July 11, 2024
    Inventors: Yoshiyuki KUROKAWA, Hiromichi GODO, Kazuki TSUDA, Kouhei TOYOTAKA, Satoru OHSHITA, Hidefumi RIKIMARU, Hideki UOCHI
  • Publication number: 20240237435
    Abstract: A semiconductor device with reduced circuit area is provided. The semiconductor device includes first and second cell arrays and a first converter circuit. The first cell array includes a first cell and a second cell in the same row, and the second cell array includes third and fourth cells in the same row. The first cell is electrically connected to first and second wirings, the second cell is electrically connected to the first and third wirings, the third cell is electrically connected to fourth and sixth wirings, and the fourth cell is electrically connected to fifth and seventh wirings. The sixth wiring is electrically connected to the seventh wiring. The first to fourth cells each have a function of outputting current corresponding to a product of retained data and input data. Specifically, the first cell, the second cell, the third cell, and the fourth cell output current to the second wiring, the third wiring, the sixth wiring, and the seventh wiring, respectively.
    Type: Application
    Filed: April 20, 2022
    Publication date: July 11, 2024
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuki TSUDA, Hidefumi RIKIMARU, Satoru OHSHITA, Hiromichi GODO, Yoshiyuki KUROKAWA
  • Publication number: 20240237374
    Abstract: An electronic device having an eye tracking function is provided. The electronic device includes a display device and an optical system. The display device includes a first light-emitting element, a second light-emitting element, a sensor portion, and a driver circuit portion. The sensor portion includes a light-receiving element. The first light-emitting element has a function of emitting infrared light or visible light. The second light-emitting element has a function of emitting light of a color different from that of light emitted from the first light-emitting element. When the first light-emitting element emits infrared light, the light-receiving element has a function of detecting the infrared light that is emitted from the first light-emitting element and reflected by an eyeball of a user.
    Type: Application
    Filed: February 24, 2022
    Publication date: July 11, 2024
    Inventors: Hiromichi GODO, Yoshiyuki KUROKAWA, Kouhei TOYOTAKA, Kazuki TSUDA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Publication number: 20240231756
    Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a cell array performing a product-sum operation of a first layer and a product-sum operation of a second layer in an artificial neural network, a first circuit from which first data is input to the cell array, and a second circuit to which second data is output from the cell array. The cell array includes a plurality of cells. The cell array includes a first region and a second region. In a first period, the first region is supplied with the t-th (t is a natural number greater than or equal to 2) first data from the first circuit and outputs the t-th second data according to the product-sum operation of the first layer to the second circuit. In the first period, the second region is supplied with the (t+1)-th first data from the first circuit and outputs the (t+1)-th second data according to the product-sum operation of the second layer to the first circuit.
    Type: Application
    Filed: February 24, 2022
    Publication date: July 11, 2024
    Inventors: Yoshiyuki KUROKAWA, Hiromichi GODO, Kazuki TSUDA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Publication number: 20240215425
    Abstract: A display apparatus having a novel structure is provided. A plurality of display panels, a fixing member having a curved surface, and a housing storing the fixing member are included. The display panel includes a display portion including a pixel circuit, a non-display portion provided to surround the display portion, a gate driver circuit for driving the pixel circuit, and a source driver circuit. The gate driver circuit is provided at a position overlapping with the display portion. The source driver circuit is provided at a position overlapping with the non-display portion. The plurality of display panels are fixed along the curved surface of the fixing member.
    Type: Application
    Filed: April 25, 2022
    Publication date: June 27, 2024
    Inventors: Hiromichi GODO, Kazuki TSUDA, Hidefumi RIKIMARU, Yoshiyuki KUROKAWA
  • Publication number: 20240143441
    Abstract: To provide an operation method of a semiconductor device in which a variation in arithmetic operation results is reduced. The semiconductor device includes first and second cell arrays and first to fifth circuits. First, third standard data is written from the fourth circuit to the second cell array, and first standard data is written from the first circuit to the first cell array. Then, second standard data is transmitted from the second circuit to the first cell array, a result of a product-sum operation of the first standard data and the second standard data is input from the first cell array to the third circuit, and fourth standard data corresponding to the result of the product-sum operation is transmitted from the third circuit to the second cell array.
    Type: Application
    Filed: October 20, 2023
    Publication date: May 2, 2024
    Inventors: Hidefumi RIKIMARU, Seiko INOUE, Hiromichi GODO, Yoshiyuki KUROKAWA
  • Publication number: 20240134605
    Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a cell array performing a product-sum operation of a first layer and a product-sum operation of a second layer in an artificial neural network, a first circuit from which first data is input to the cell array, and a second circuit to which second data is output from the cell array. The cell array includes a plurality of cells. The cell array includes a first region and a second region. In a first period, the first region is supplied with the t-th (t is a natural number greater than or equal to 2) first data from the first circuit and outputs the t-th second data according to the product-sum operation of the first layer to the second circuit. In the first period, the second region is supplied with the (t+1)-th first data from the first circuit and outputs the (t+1)-th second data according to the product-sum operation of the second layer to the first circuit.
    Type: Application
    Filed: February 24, 2022
    Publication date: April 25, 2024
    Inventors: Yoshiyuki KUROKAWA, Hiromichi GODO, Kazuki TSUDA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Publication number: 20240138167
    Abstract: An electronic device having an eye tracking function is provided. The electronic device includes a display device and an optical system. The display device includes a first light-emitting element, a second light-emitting element, a sensor portion, and a driver circuit portion. The sensor portion includes a light-receiving element. The first light-emitting element has a function of emitting infrared light or visible light. The second light-emitting element has a function of emitting light of a color different from that of light emitted from the first light-emitting element. When the first light-emitting element emits infrared light, the light-receiving element has a function of detecting the infrared light that is emitted from the first light-emitting element and reflected by an eyeball of a user.
    Type: Application
    Filed: February 24, 2022
    Publication date: April 25, 2024
    Inventors: Hiromichi GODO, Yoshiyuki KUROKAWA, Kouhei TOYOTAKA, Kazuki TSUDA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Patent number: 11921919
    Abstract: To provide a novel electronic device. The electronic device includes a housing and a display device. The display device includes a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are provided in different layers. The first layer includes a driver circuit and an arithmetic circuit. The second layer includes pixel circuits and a cell array. The third layer includes light-receiving devices and light-emitting devices. The pixel circuits each have a function of controlling light emission of the light-emitting device. The driver circuit has a function of controlling the pixel circuits. The arithmetic circuit has a function of performing arithmetic processing on the basis of first data corresponding to currents output from the light-receiving devices and second data corresponding to a potential held in the cell array.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: March 5, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Hiromichi Godo, Kouhei Toyotaka, Kazuki Tsuda, Satoru Ohshita, Hidefumi Rikimaru
  • Publication number: 20230369329
    Abstract: A semiconductor device with low power consumption is provided. The semiconductor device includes a first layer and a second layer. The first layer includes a first cell and a first to a third circuit, and the second layer includes a second cell and a fourth and a fifth circuit. The first, second, and fourth circuits each have a function of converting digital data into analog current. The first cell calculates a product of a value from the first current and a value from the second circuit and inputs a calculation result into a third circuit as current. The third circuit generates analog current from the input current. The second cell calculates a product of a value from the third circuit and a value from the fourth circuit and inputs a calculation result into the fifth circuit as current. The fifth circuit generates analog current from the input current.
    Type: Application
    Filed: May 3, 2023
    Publication date: November 16, 2023
    Inventors: Yoshiyuki KUROKAWA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Publication number: 20230353163
    Abstract: A novel semiconductor device is provided. An analog signal is converted into a digital signal using a comparison portion comparing two current values, a control portion, and a current output digital-analog conversion portion. The control portion has a function of generating a sign bit showing a magnitude relation between the two current values, a function of converting a difference between the two current values into a digital signal by successive approximation, and a function of outputting the sign bit and the digital signal.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 2, 2023
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuro KANEMURA, Yoshiyuki KUROKAWA, Hiromichi GODO, Kazuki TSUDA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Publication number: 20230317176
    Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes memory layers and a driver circuit layer. The memory layers are stacked over the driver circuit layer and each include a memory cell array including a plurality of memory cells. Writing or reading of data to or from one of the memory cells is controlled with a write word line, a read word line, a write bit line, and a read bit line. The driver circuit layer includes a driver circuit portion configured to drive the write word line, the read word line, the write bit line, and the read bit line; and an arithmetic circuit portion. The driver circuit portion includes a plurality of driver circuits configured to control data writing or reading on the memory cell array basis. The arithmetic circuit portion is a circuit configured to perform arithmetic processing using the data retained in the memory cell array provided in each of the memory layers and read through the driver circuit portion.
    Type: Application
    Filed: March 23, 2023
    Publication date: October 5, 2023
    Inventors: Yoshiyuki KUROKAWA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Publication number: 20230284429
    Abstract: Provided is a semiconductor device having a novel structure. A first transistor, a second transistor, a third transistor, and a capacitor are included. The first transistor has a function of retaining a first potential corresponding to first data supplied to a gate of the third transistor through the first transistor when being in an off state. The capacitor has a function of changing the first potential retained in the gate of the third transistor into a second potential in accordance with a change in potential corresponding to second data supplied to one electrode of the capacitor. The second transistor has a function of setting a potential of one of a source and a drain of the third transistor to a potential corresponding to a potential of a gate of the second transistor. The third transistor has a function of supplying output current corresponding to a potential of the gate of the third transistor to the other of the source and the drain of the third transistor.
    Type: Application
    Filed: July 19, 2021
    Publication date: September 7, 2023
    Inventors: Hiromichi GODO, Kazuki TSUDA, Yoshiyuki KUROKAWA, Satoru OHSHITA, Takuro KANEMURA, Hidefumi RIKIMARU
  • Publication number: 20230273637
    Abstract: A control circuit of a secondary battery with a novel structure is provided. The control circuit of a secondary battery includes a first transistor, a first voltage generation circuit generating a first voltage, and a second voltage generation circuit generating a second voltage. The first voltage generation circuit includes a second transistor and a first capacitor. The second voltage generation circuit includes a third transistor and a second capacitor. The difference between the first voltage and the second voltage is set in accordance with the threshold voltage of the first transistor. When the first transistor includes a back gate, a voltage retention circuit having a function of retaining the voltage of the back gate is included. The voltage retention circuit includes a fourth transistor and a third capacitor. The third capacitor includes a ferroelectric layer between a pair of electrodes.
    Type: Application
    Filed: August 25, 2021
    Publication date: August 31, 2023
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki KUROKAWA, Kazuki TSUDA, Hiromichi GODO, Satoru OHSHITA, Takuro KANEMURA, Hidefumi RIKIMARU, Takayuki IKEDA, Yuto YAKUBO, Shunpei YAMAZAKI
  • Patent number: 11594176
    Abstract: A semiconductor device with a high driving speed is provided. The semiconductor device includes first to fourth cells, a converter circuit, and first to fourth wirings. The first and second cells make a first current and a second current each corresponding to the product of first data and second data flow in the first wiring and the second wiring, respectively. The third and fourth cells make base currents in the same amount flow in the first and second wirings. The converter circuit outputs, from an output terminal thereof, a voltage corresponding to the differential current between the sum of the first current and the base current flowing in the first wiring and the sum of the second current and the base current flowing in the second wiring.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: February 28, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Yoshiyuki Kurokawa, Kazuki Tsuda, Satoru Ohshita, Hidefumi Rikimaru
  • Publication number: 20220293049
    Abstract: A semiconductor device with a high driving speed is provided. The semiconductor device includes first to fourth cells, a converter circuit, and first to fourth wirings. The first and second cells make a first current and a second current each corresponding to the product of first data and second data flow in the first wiring and the second wiring, respectively. The third and fourth cells make base currents in the same amount flow in the first and second wirings. The converter circuit outputs, from an output terminal thereof, a voltage corresponding to the differential current between the sum of the first current and the base current flowing in the first wiring and the sum of the second current and the base current flowing in the second wiring.
    Type: Application
    Filed: March 4, 2022
    Publication date: September 15, 2022
    Inventors: Hiromichi GODO, Yoshiyuki KUROKAWA, Kazuki TSUDA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Publication number: 20220270548
    Abstract: To provide a novel electronic device. The electronic device includes a housing and a display device. The display device includes a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are provided in different layers. The first layer includes a driver circuit and an arithmetic circuit. The second layer includes pixel circuits and a cell array. The third layer includes light-receiving devices and light-emitting devices. The pixel circuits each have a function of controlling light emission of the light-emitting device. The driver circuit has a function of controlling the pixel circuits. The arithmetic circuit has a function of performing arithmetic processing on the basis of first data corresponding to currents output from the light-receiving devices and second data corresponding to a potential held in the cell array.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 25, 2022
    Inventors: Yoshiyuki Kurokawa, Hiromichi Godo, Kouhei Toyotaka, Kazuki Tsuda, Satoru Ohshita, Hidefumi Rikimaru