Patents by Inventor Hidefumi Takaya

Hidefumi Takaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10522627
    Abstract: A semiconductor device may be provided with a semiconductor substrate, an upper electrode, a lower electrode and a gate electrode provided within a trench via a gate insulator film. The semiconductor substrate may include a p-type body layer being in contact with the upper electrode, an n-type drift layer intervening between the body layer and the lower electrode, a p-type floating region provided along a bottom surface of the trench, and a p-type connection region extending between the body layer and the floating region along a side surface of the trench. The trench may include a first section where the connection region is not provided and a second section where the connection region is provided. An inclination angle of the side surface of the trench in the second section may be greater than an inclination angle of the side surface of the trench in the first section.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: December 31, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidefumi Takaya, Yasushi Urakami, Narumasa Soejima
  • Publication number: 20190067420
    Abstract: A semiconductor device may be provided with a semiconductor substrate, an upper electrode, a lower electrode and a gate electrode provided within a trench via a gate insulator film. The semiconductor substrate may include a p-type body layer being in contact with the upper electrode, an n-type drift layer intervening between the body layer and the lower electrode, a p-type floating region provided along a bottom surface of the trench, and a p-type connection region extending between the body layer and the floating region along a side surface of the trench. The trench may include a first section where the connection region is not provided and a second section where the connection region is provided. An inclination angle of the side surface of the trench in the second section may be greater than an inclination angle of the side surface of the trench in the first section.
    Type: Application
    Filed: July 5, 2018
    Publication date: February 28, 2019
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidefumi TAKAYA, Yasushi URAKAMI, Narumasa SOEJIMA
  • Patent number: 10153345
    Abstract: A method for manufacturing an insulated gate switching device is provided. The method includes: forming a first trench in a surface of a first SiC semiconductor layer; implanting p-type impurities into a bottom surface of the first trench; depositing a second SiC semiconductor layer on an inner surface of the first trench to form a second trench; and forming a gate insulating layer, a gate electrode, a first region and a body region so that the gate insulating layer covers an inner surface of the second trench, the gate electrode is located in the second trench, the first region is of n-type and in contact with the gate insulating layer, the body region is of p-type, separated from the implanted region, and in contact with the gate insulating layer under the first region.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: December 11, 2018
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hidefumi Takaya, Shoji Mizuno, Yukihiko Watanabe, Sachiko Aoi
  • Patent number: 10134593
    Abstract: A semiconductor device includes: a substrate having a cell region with a semiconductor element and an outer peripheral region; and a drift layer on the substrate. The semiconductor element includes a base region, a source region, a trench gate structure, a deep layer deeper than a gate trench, a source electrode, and a drain electrode. The outer peripheral region has a recess portion in which the drift layer are exposed, and a guard ring layer. The guard ring layer includes multiple guard ring trenches having a frame shape, surrounding the cell region and arranged on an exposed surface of the drift layer, and a first guard ring in the guard ring trenches. Each of the linear deep trenches has a width equal to a width of each of the linear guard ring trenches.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: November 20, 2018
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takeshi Endo, Atsuya Akiba, Yuichi Takeuchi, Hidefumi Takaya, Sachiko Aoi
  • Publication number: 20180182889
    Abstract: An n-type drift region, a p-type first body region and a p-type contact region are formed on an SiC substrate by epitaxial growth. An opening is formed within the contact region by etching such that the first body region is exposed through the opening, and a p-type second body region is formed on the first body region exposed through the opening by epitaxial growth. An n-type source region is formed by epitaxial growth, and an opening is formed within a part of the source region located on the contact region by etching such that the contact region is exposed through the opening. A trench is formed by etching such that the trench extends from the source region to the drift region through the opening of the contact region, and a gate insulating film and a gate electrode are formed within the trench.
    Type: Application
    Filed: November 17, 2017
    Publication date: June 28, 2018
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hidefumi Takaya, Yasushi Urakami, Yukihiko Watanabe
  • Publication number: 20180175149
    Abstract: A method for manufacturing an insulated gate switching device is provided. The method includes: forming a first trench in a surface of a first SiC semiconductor layer; implanting p-type impurities into a bottom surface of the first trench; depositing a second SiC semiconductor layer on an inner surface of the first trench to form a second trench; and forming a gate insulating layer, a gate electrode, a first region and a body region so that the gate insulating layer covers an inner surface of the second trench, the gate electrode is located in the second trench, the first region is of n-type and in contact with the gate insulating layer, the body region is of p-type, separated from the implanted region, and in contact with the gate insulating layer under the first region.
    Type: Application
    Filed: June 3, 2016
    Publication date: June 21, 2018
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hidefumi TAKAYA, Shoji MIZUNO, Yukihiko WATANABE, Sachiko AOI
  • Publication number: 20180151366
    Abstract: A semiconductor device includes: a substrate having a cell region with a semiconductor element and an outer peripheral region; and a drift layer on the substrate. The semiconductor element includes a base region, a source region, a trench gate structure, a deep layer deeper than a gate trench, a source electrode, and a drain electrode. The outer peripheral region has a recess portion in which the drift layer are exposed, and a guard ring layer. The guard ring layer includes multiple guard ring trenches having a frame shape, surrounding the cell region and arranged on an exposed surface of the drift layer, and a first guard ring in the guard ring trenches. Each of the linear deep trenches has a width equal to a width of each of the linear guard ring trenches.
    Type: Application
    Filed: April 5, 2016
    Publication date: May 31, 2018
    Inventors: Takeshi ENDO, Atsuya AKIBA, Yuichi TAKEUCHI, Hidefumi TAKAYA, Sachiko AOI
  • Patent number: 9853139
    Abstract: A semiconductor device provided herein includes: a fourth region of a p-type being in contact with a lower end of the gate trench; a termination trench provided in the front surface in a range outside the second region; a lower end p-type region of the p-type being in contact with a lower end of the termination trench; a lateral p-type region of the p-type being in contact with a lateral surface of the termination trench on an outer circumferential side, connected to the lower end p-type region, and exposed on the front surface; and a plurality of guard ring regions provided on the outer circumferential side with respect to the lateral p-type region and exposed on the front surface.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: December 26, 2017
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hidefumi Takaya, Jun Saito, Akitaka Soeno, Toshimasa Yamamoto, Narumasa Soejima
  • Patent number: 9847414
    Abstract: A semiconductor device provided herein includes a trench in which a gate insulating layer (GIL) and a gate electrode are located. A step is provided in a lateral surface of the trench. The step surface descends toward a center of the trench. First and second regions are of a first conductivity type. A body region, a lateral region and a bottom region are of a second conductivity type. The first region, a body region, and the second region are in contact with the GIL at the upper lateral surface of the trench. The second region is in contact with the GIL at the lower lateral surface of the trench. A lateral region is in contact with the GIL at the lower lateral surface. A bottom region is in contact with the GIL at the bottom surface of the trench.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: December 19, 2017
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hidefumi Takaya, Shinichiro Miyahara, Katsuhiro Kutsuki, Sachiko Aoi
  • Patent number: 9818860
    Abstract: An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: November 14, 2017
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuichi Takeuchi, Naohiro Suzuki, Masahiro Sugimoto, Hidefumi Takaya, Akitaka Soeno, Jun Morimoto, Narumasa Soejima, Yukihiko Watanabe
  • Patent number: 9640651
    Abstract: A semiconductor device includes a termination trench surrounding a region in which a plurality of gate trenches is provided; a p-type lower end region being in contact with a lower end of the termination trench; a p-type outer circumference region being in contact with the termination trench from an outer circumferential side and exposed on a surface of the semiconductor device; a plurality of guard ring regions of a p-type provided on an outer circumferential side of the p-type outer circumference region and exposed on the surface; and an n-type outer circumference region separating the p-type outer circumference region from the guard ring regions and separating the guard ring regions from each another.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: May 2, 2017
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hidefumi Takaya, Jun Saito, Akitaka Soeno, Kimimori Hamada, Shoji Mizuno, Sachiko Aoi, Yukihiko Watanabe
  • Patent number: 9627248
    Abstract: An insulating gate type semiconductor device being capable of easily depleting an outer periphery region is provided. The insulating gate type semiconductor device includes: first to fourth outer periphery trenches formed in a front surface of a semiconductor substrate; insulating layers located in the outer periphery trenches; fifth semiconductor regions being of a second conductive type and formed in ranges exposed to bottom surfaces of the outer periphery trenches; and a connection region connecting the fifth semiconductor region exposed to the bottom surface of the second outer periphery trench to the fifth semiconductor region exposed to the bottom surface of the third outer periphery trench. A clearance between the second and third outer periphery trenches is wider than each of a clearance between the first and second outer periphery trenches and a clearance between the third and fourth outer periphery trenches.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: April 18, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Jun Saito, Kimimori Hamada, Akitaka Soeno, Hidefumi Takaya, Sachiko Aoi, Toshimasa Yamamoto
  • Publication number: 20170084735
    Abstract: An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Inventors: Yuichi TAKEUCHI, Naohiro SUZUKI, Masahiro SUGIMOTO, Hidefumi TAKAYA, Akitaka SOENO, Jun MORIMOTO, Narumasa SOEJIMA, Yukihiko WATANABE
  • Publication number: 20170018643
    Abstract: A semiconductor device provided herein includes: a fourth region of a p-type being in contact with a lower end of the gate trench; a termination trench provided in the front surface in a range outside the second region; a lower end p-type region of the p-type being in contact with a lower end of the termination trench; a lateral p-type region of the p-type being in contact with a lateral surface of the termination trench on an outer circumferential side, connected to the lower end p-type region, and exposed on the front surface; and a plurality of guard ring regions provided on the outer circumferential side with respect to the lateral p-type region and exposed on the front surface.
    Type: Application
    Filed: February 10, 2015
    Publication date: January 19, 2017
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hidefumi TAKAYA, Jun SAITO, Akitaka SOENO, Toshimasa YAMAMOTO, Narumasa SOEJIMA
  • Publication number: 20170011952
    Abstract: An insulating gate type semiconductor device being capable of easily depleting an outer periphery region is provided. The insulating gate type semiconductor device includes: first to fourth outer periphery trenches formed in a front surface of a semiconductor substrate; insulating layers located in the outer periphery trenches; fifth semiconductor regions being of a second conductive type and formed in ranges exposed to bottom surfaces of the outer periphery trenches; and a connection region connecting the fifth semiconductor region exposed to the bottom surface of the second outer periphery trench to the fifth semiconductor region exposed to the bottom surface of the third outer periphery trench. A clearance between the second and third outer periphery trenches is wider than each of a clearance between the first and second outer periphery trenches and a clearance between the third and fourth outer periphery trenches.
    Type: Application
    Filed: February 5, 2015
    Publication date: January 12, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Jun SAITO, Kimimori HAMADA, Akitaka SOENO, Hidefumi TAKAYA, Sachiko AOI, Toshimasa YAMAMOTO
  • Publication number: 20170012122
    Abstract: A semiconductor device includes a termination trench surrounding a region in which a plurality of gate trenches is provided; a p-type lower end region being in contact with a lower end of the termination trench; a p-type outer circumference region being in contact with the termination trench from an outer circumferential side and exposed on a surface of the semiconductor device; a plurality of guard ring regions of a p-type provided on an outer circumferential side of the p-type outer circumference region and exposed on the surface; and an n-type outer circumference region separating the p-type outer circumference region from the guard ring regions and separating the guard ring regions from each another.
    Type: Application
    Filed: October 6, 2014
    Publication date: January 12, 2017
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hidefumi TAKAYA, Jun SAITO, Akitaka SOENO, Kimimori HAMADA, Shoji MIZUNO, Sachiko AOI, Yukihiko WATANABE
  • Patent number: 9543428
    Abstract: An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: January 10, 2017
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuichi Takeuchi, Naohiro Suzuki, Masahiro Sugimoto, Hidefumi Takaya, Akitaka Soeno, Jun Morimoto, Narumasa Soejima, Yukihiko Watanabe
  • Patent number: 9391190
    Abstract: A FET incorporating a Schottky diode has a structure allowing the ratio of an area in which the Schottky diode is formed and an area in which the FET is formed to be freely adjusted. A trench extending for a long distance is utilized. Schottky electrodes are interposed at positions appearing intermittently in the longitudinal direction of the trench. By taking advantage of the growth rate of a thermal oxide film formed on SiC being slower, and the growth rate of a thermal oxide film formed on polysilicon being faster, a structure can be obtained in which insulating film is formed between gate electrodes and Schottky electrodes, between the gate electrodes and a source region, between the gate electrodes and a body region, and between the gate electrodes and a drain region, and in which insulating film is not formed between the Schottky electrodes and the drain region.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: July 12, 2016
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Yukihiko Watanabe, Sachiko Aoi, Hidefumi Takaya, Atsuya Akiba
  • Publication number: 20160149029
    Abstract: A semiconductor device includes a semiconductor substrate including a trench, a gate insulating layer, and a gate electrode. A step is arranged in a side surface of the trench. The semiconductor substrate includes first and second regions, a body region, and a side region. The body region extends from a position being in contact with the first region to a position located on the lower side with respect to the step. The body region is in contact with the gate insulating layer at a portion of the upper side surface located on a lower side with respect to the first region. The second region is located on a lower side of the body region and in contact with the gate insulating layer at the lower side surface. The side region is in contact with the gate insulating layer at the step surface and connected to the second region.
    Type: Application
    Filed: November 12, 2015
    Publication date: May 26, 2016
    Inventors: Hidefumi TAKAYA, Katsuhiro KUTSUKI, Sachiko AOI, Shinichiro MIYAHARA
  • Publication number: 20160141409
    Abstract: A semiconductor device provided herein includes a trench in which a gate insulating layer (GIL) and a gate electrode are located. A step is provided in a lateral surface of the trench. The step surface descends toward a center of the trench. First and second regions are of a first conductivity type. A body region, a lateral region and a bottom region are of a second conductivity type. The first region, a body region, and the second region are in contact with the GIL at the upper lateral surface of the trench. The second region is in contact with the GIL at the lower lateral surface of the trench. A lateral region is in contact with the GIL at the lower lateral surface. A bottom region is in contact with the GIL at the bottom surface of the trench.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 19, 2016
    Inventors: Hidefumi Takaya, Shinichiro Miyahara, Katsuhiro Kutsuki, Sachiko Aoi