Patents by Inventor Hidefumi Takaya

Hidefumi Takaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9391190
    Abstract: A FET incorporating a Schottky diode has a structure allowing the ratio of an area in which the Schottky diode is formed and an area in which the FET is formed to be freely adjusted. A trench extending for a long distance is utilized. Schottky electrodes are interposed at positions appearing intermittently in the longitudinal direction of the trench. By taking advantage of the growth rate of a thermal oxide film formed on SiC being slower, and the growth rate of a thermal oxide film formed on polysilicon being faster, a structure can be obtained in which insulating film is formed between gate electrodes and Schottky electrodes, between the gate electrodes and a source region, between the gate electrodes and a body region, and between the gate electrodes and a drain region, and in which insulating film is not formed between the Schottky electrodes and the drain region.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: July 12, 2016
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Yukihiko Watanabe, Sachiko Aoi, Hidefumi Takaya, Atsuya Akiba
  • Publication number: 20160149029
    Abstract: A semiconductor device includes a semiconductor substrate including a trench, a gate insulating layer, and a gate electrode. A step is arranged in a side surface of the trench. The semiconductor substrate includes first and second regions, a body region, and a side region. The body region extends from a position being in contact with the first region to a position located on the lower side with respect to the step. The body region is in contact with the gate insulating layer at a portion of the upper side surface located on a lower side with respect to the first region. The second region is located on a lower side of the body region and in contact with the gate insulating layer at the lower side surface. The side region is in contact with the gate insulating layer at the step surface and connected to the second region.
    Type: Application
    Filed: November 12, 2015
    Publication date: May 26, 2016
    Inventors: Hidefumi TAKAYA, Katsuhiro KUTSUKI, Sachiko AOI, Shinichiro MIYAHARA
  • Publication number: 20160141409
    Abstract: A semiconductor device provided herein includes a trench in which a gate insulating layer (GIL) and a gate electrode are located. A step is provided in a lateral surface of the trench. The step surface descends toward a center of the trench. First and second regions are of a first conductivity type. A body region, a lateral region and a bottom region are of a second conductivity type. The first region, a body region, and the second region are in contact with the GIL at the upper lateral surface of the trench. The second region is in contact with the GIL at the lower lateral surface of the trench. A lateral region is in contact with the GIL at the lower lateral surface. A bottom region is in contact with the GIL at the bottom surface of the trench.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 19, 2016
    Inventors: Hidefumi Takaya, Shinichiro Miyahara, Katsuhiro Kutsuki, Sachiko Aoi
  • Publication number: 20160087094
    Abstract: A semiconductor device includes a semiconductor substrate having a main cell region and a sense cell region. A separation trench separating a main second semiconductor region from a sense second semiconductor region is provided in an upper surface of the semiconductor substrate. The semiconductor substrate includes a separation fourth semiconductor region being of a second conductivity type and separated from the main second semiconductor region and the sense second semiconductor substrate by a third semiconductor region.
    Type: Application
    Filed: September 14, 2015
    Publication date: March 24, 2016
    Inventors: Hidefumi Takaya, Jun Saito, Sachiko Aoi, Yukihiko Watanabe, Shoji Mizuno, Shinichiro Miyahara
  • Patent number: 9281396
    Abstract: A trench structure which is capable of promoting extension of a depletion layer and hardly causes thermal stress is provided. A semiconductor device includes a semiconductor substrate. A plurality of loop trenches is formed on the surface of the semiconductor substrate. Each loop trench is configured to extend so as to surround a region smaller than the region where a plurality of gate trenches is formed. Each loop trench is separated from other loop trenches. A second insulating layer is located in each loop trench. P-type fourth regions are formed in the semiconductor substrate. Each fourth region is in contact with a bottom surface of corresponding one of the loop trenches and is configured to extend along the corresponding one of the loop trenches.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: March 8, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidefumi Takaya, Katsuhiro Kutsuki
  • Patent number: 9276075
    Abstract: A semiconductor device has a semiconductor substrate including a body region, a drift region, a trench that extends from a surface of the semiconductor substrate into the drift region through the body region, and a source region located adjacent to the trench in a range exposed to the surface of the semiconductor substrate, the source region being isolated from the drift region by the body region. A specific layer is disposed on a bottom of the trench, and it has a characteristic of forming a depletion layer at a junction between the specific layer and the drift region. An insulating layer covers an upper surface of the specific layer and a sidewall of the trench. A conductive portion is formed on a part of the side wall of the trench. The conductive portion is joined to the specific layer, and reaches the surface of the semiconductor substrate.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: March 1, 2016
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hidefumi Takaya, Hideo Matsuki, Naohiro Suzuki, Tsuyoshi Ishikawa, Narumasa Soejima, Yukihiko Watanabe
  • Patent number: 9257501
    Abstract: A semiconductor substrate of a semiconductor device includes a first conductive body region that is formed in the element region; a second conductive drift region that is formed in the element region; a gate electrode that is formed in the element region, that is arranged in a gate trench, and that faces the body region; an insulating body that is formed in the element region and is arranged between the gate electrode and an inside wall of the gate trench; a first conductive floating region that is formed in the element region and that is surrounded by the drift region; a first voltage-resistance retaining structure that is formed in the peripheral region and that surrounds the element region; and a gate pad that is formed in the peripheral region, and is electrically connected to the gate electrode in a position on the element region-side of the first voltage-resistance retaining structure.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: February 9, 2016
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hidefumi Takaya, Masaru Nagao, Narumasa Soejima
  • Patent number: 9214526
    Abstract: A semiconductor device includes: a drift layer having a first conductivity type; a body layer having a second conductivity type; a first semiconductor region having the first conductivity type; a gate insulation film; a trench gate electrode; a first main electrode; a second semiconductor region having the second conductivity type; and a conductor region. The first main electrode is electrically connected with the body layer and the first semiconductor region. The second semiconductor region is disposed on a bottom part of the gate trench, and is surrounded by the drift layer. The conductor region is configured to electrically connect the first main electrode with the second semiconductor region and is configured to equalize, when the semiconductor device is in an off-state, a potential of the second semiconductor region and a potential of the first main electrode.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: December 15, 2015
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hidefumi Takaya, Yukihiko Watanabe, Sachiko Aoi, Atsuya Akiba
  • Patent number: 9136372
    Abstract: In a silicon carbide semiconductor device, a plurality of trenches has a longitudinal direction in one direction and is arranged in a stripe pattern. Each of the trenches has first and second sidewalls extending in the longitudinal direction. The first sidewall is at a first acute angle to one of a (11-20) plane and a (1-100) plane, the second sidewall is at a second acute angle to the one of the (11-20) plane and the (1-100) plane, and the first acute angle is smaller than the second acute angle. A first conductivity type region is in contact with only the first sidewall in the first and second sidewalls of each of the trenches, and a current path is formed on only the first sidewall in the first and second sidewalls.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: September 15, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shinichiro Miyahara, Masahiro Sugimoto, Hidefumi Takaya, Yukihiko Watanabe, Narumasa Soejima, Tsuyoshi Ishikawa
  • Patent number: 9064952
    Abstract: A semiconductor device 10 includes an element domain 40 and a termination domain 50 that surrounds the element domain 40. The element domain 40 and the termination domain 50 respectively include a second conductive type drift region 18. A gate trench 38 may be provided in the element domain 40. The termination domain 50 may be provided with a termination trench 22 surrounding the element domain. A first conductive type floating region surrounded by the drift region 18 is not provided at a bottom of the gate trench 38, and a first conductive type floating region 20 surrounded by the drift region 18 is provided at a bottom of the termination trench 22.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: June 23, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Hidefumi Takaya
  • Publication number: 20150171175
    Abstract: A semiconductor device includes: a drift layer having a first conductivity type; a body layer having a second conductivity type; a first semiconductor region having the first conductivity type; a gate insulation film; a trench gate electrode; a first main electrode; a second semiconductor region having the second conductivity type; and a conductor region. The first main electrode is electrically connected with the body layer and the first semiconductor region. The second semiconductor region is disposed on a bottom part of the gate trench, and is surrounded by the drift layer. The conductor region is configured to electrically connect the first main electrode with the second semiconductor region and is configured to equalize, when the semiconductor device is in an off-state, a potential of the second semiconductor region and a potential of the first main electrode.
    Type: Application
    Filed: December 2, 2014
    Publication date: June 18, 2015
    Inventors: Hidefumi TAKAYA, Yukihiko WATANABE, Sachiko AOI, Atsuya AKIBA
  • Publication number: 20150129957
    Abstract: A trench structure which is capable of promoting extension of a depletion layer and hardly causes thermal stress is provided. A semiconductor device includes a semiconductor substrate. A plurality of loop trenches is formed on the surface of the semiconductor substrate. Each loop trench is configured to extend so as to surround a region smaller than the region where a plurality of gate trenches is formed. Each loop trench is separated from other loop trenches. A second insulating layer is located in each loop trench. P-type fourth regions are formed in the semiconductor substrate. Each fourth region is in contact with a bottom surface of corresponding one of the loop trenches and is configured to extend along the corresponding one of the loop trenches.
    Type: Application
    Filed: October 2, 2014
    Publication date: May 14, 2015
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidefumi TAKAYA, Katsuhiro KUTSUKI
  • Publication number: 20150115286
    Abstract: An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.
    Type: Application
    Filed: June 6, 2013
    Publication date: April 30, 2015
    Applicant: Denso Corporation
    Inventors: Yuichi Takeuchi, Naohiro Suzuki, Masahiro Sugimoto, Hidefumi Takaya, Akitaka Soeno, Jun Morimoto, Narumasa Soejima, Yukihiko Watanabe
  • Patent number: 8975139
    Abstract: A manufacturing method of a silicon carbide semiconductor device includes: forming a drift layer on a silicon carbide substrate; forming a base layer on or in a surface portion of the drift layer; forming a source region in a surface portion of the base layer; forming a trench to penetrate the base layer and to reach the drift layer; forming a gate electrode on a gate insulation film in the trench; forming a source electrode electrically connected to the source region and the base layer; and forming a drain electrode on a back surface of the substrate. The forming of the trench includes: flattening a substrate surface; and etching to form the trench after flattening.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: March 10, 2015
    Assignees: DENSO CORPORATION, Toyota Jidosha Kabushiki Kaisha
    Inventors: Shinichiro Miyahara, Toshimasa Yamamoto, Hidefumi Takaya, Masahiro Sugimoto, Yukihiko Watanabe, Narumasa Soejima, Tsuyoshi Ishikawa
  • Patent number: 8952430
    Abstract: The present application relates to technology for improving a withstand voltage of a semiconductor device. The semiconductor device includes a termination area that surrounds a cell area. The cell area is provided with a plurality of main trenches. The termination area is provided with one or more termination trenches surrounding the cell area. A termination trench is disposed at an innermost circumference of one or more termination trenches. A body region is disposed on a surface of a drift region. Each main trench reaches the drift region. A gate electrode is provided within each main trench. The termination trench reaches the drift region. Sidewalls and a bottom surface of the termination trench are covered with a insulating layer. A surface of the insulating layer covering the bottom surface of the termination trench is covered with a buried electrode. A gate potential is applied to the buried electrode.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: February 10, 2015
    Assignees: Denso Corporation, Toyota Jidosha Kabushiki Kaisha
    Inventors: Hidefumi Takaya, Hideo Matsuki, Naohiro Suzuki, Tsuyoshi Ishikawa
  • Publication number: 20150021680
    Abstract: A FET incorporating a Schottky diode has a structure allowing the ratio of an area in which the Schottky diode is formed and an area in which the FET is formed to be freely adjusted. A trench extending for a long distance is utilized. Schottky electrodes are interposed at positions appearing intermittently in the longitudinal direction of the trench. By taking advantage of the growth rate of a thermal oxide film formed on SiC being slower, and the growth rate of a thermal oxide film formed on polysilicon being faster, a structure can be obtained in which insulating film is formed between gate electrodes and Schottky electrodes, between the gate electrodes and a source region, between the gate electrodes and a body region, and between the gate electrodes and a drain region, and in which insulating film is not formed between the Schottky electrodes and the drain region.
    Type: Application
    Filed: June 9, 2014
    Publication date: January 22, 2015
    Inventors: Yukihiko WATANABE, Sachiko AOI, Hidefumi TAKAYA, Atsuya AKIBA
  • Patent number: 8933483
    Abstract: Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ? i = 1 n ? ( R Mi × k Mi ) - ? i = 1 n ? ( R Si × k Si ) ] / ? i = 1 n ? ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: January 13, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hidefumi Takaya, Kimimori Hamada, Yuji Nishibe
  • Patent number: 8878290
    Abstract: A semiconductor substrate of a semiconductor device includes a body region of a first conductivity type, a drift region of a second conductivity type coming into contact with a lower surface of the body region, a gate electrode that is provided in a gate trench passing through the body region and extending to the drift region and faces the body region, and a gate insulator that is provided between the gate electrode and a wall surface of the gate trench. An inverted U-shaped section is formed in a lower surface of the gate insulator, and a floating region of the first conductivity type is formed in the inverted U-shaped section. The floating region protrudes under a portion that is located at a lowermost portion in the lower surface of the gate insulator.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: November 4, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hidefumi Takaya, Narumasa Soejima
  • Publication number: 20140252465
    Abstract: A semiconductor device has a semiconductor substrate including a body region, a drift region, a trench that extends from a surface of the semiconductor substrate into the drift region through the body region, and a source region located adjacent to the trench in a range exposed to the surface of the semiconductor substrate, the source region being isolated from the drift region by the body region. A specific layer is disposed on a bottom of the trench, and it has a characteristic of forming a depletion layer at a junction between the specific layer and the drift region. An insulating layer covers an upper surface of the specific layer and a sidewall of the trench. A conductive portion is formed on a part of the side wall of the trench. The conductive portion is joined to the specific layer, and reaches the surface of the semiconductor substrate.
    Type: Application
    Filed: October 17, 2012
    Publication date: September 11, 2014
    Applicants: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidefumi Takaya, Hideo Matsuki, Naohiro Suzuki, Tsuyoshi Ishikawa, Narumasa Soejima, Yukihiko Watanabe
  • Patent number: 8809986
    Abstract: Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current. In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ? i = 1 n ? ( R Mi × k Mi ) - ? i = 1 n ? ( R Si × k Si ) ] / ? i = 1 n ? ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: August 19, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hidefumi Takaya, Kimimori Hamada, Yuji Nishibe