Patents by Inventor Hideharu Egawa

Hideharu Egawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5061983
    Abstract: A method for manufacturing a semiconductor device that includes p- and n-type regions formed on an insulating substrate, and an interconnection layer electrically coupled with these p- and n-type regions. The interconnection layer is an n-type polycrystalline silicon layer which is electrically coupled with the p- and n-type regions through a metal silicide film formed between the interconnection layer and the p- and n-type regions.
    Type: Grant
    Filed: February 28, 1989
    Date of Patent: October 29, 1991
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Hideharu Egawa, Yoshio Nishi, Kenji Maeguchi
  • Patent number: 5017994
    Abstract: A semiconductor circuit has a power source terminal set at a positive potential, a reference potential terminal set at a reference potential, a first MOS transistor whose current path is connected between the power source terminal and an output terminal, and a second MOS transistor whose current path is connected between the output terminal and the reference potential terminal. The gates of the first and second MOS transistors are commonly connected to an input terminal. The first and second MOS transistors are respectively n- and p-channel MOS transistors.
    Type: Grant
    Filed: May 1, 1989
    Date of Patent: May 21, 1991
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Hideharu Egawa, Yasoji Suzuki
  • Patent number: 4975757
    Abstract: A complementary semiconductor device includes P- and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. N-and P-channel type silicon gate field effect transistors are formed in the P-and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.
    Type: Grant
    Filed: October 20, 1987
    Date of Patent: December 4, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideharu Egawa, Koji Matsuki, Yasoji Suzuki
  • Patent number: 4883986
    Abstract: A semiconductor circuit has a power source terminal set at a positive potential, a reference potential terminal set at a reference potential, a first MOS transistor whose current path is connected between the power source terminal and an output terminal, and a second MOS transistor whose current path is connected between the output terminal and the reference potential terminal. The gates of the first and second MOS transistors are commonly connected to an input terminal. The first and second MOS transistors are respectively n- and p-channel MOS transistors.
    Type: Grant
    Filed: May 14, 1982
    Date of Patent: November 28, 1989
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Hideharu Egawa, Yasoji Suzuki
  • Patent number: 4678114
    Abstract: The invention provides a bonding wire which prevents electric short-circuiting even if it comes into contact with another bonding wire, a bonding method using the same, and a semiconductor device including the same. The bonding wire comprises a core wire made of a metal and an insulating film which surrounds it. The insulating film is eliminated from the ends of the bonding wire by thermal decomposition and scattering, while simultaneously each end of the bonding wire is connected to a bonding pad of the semiconductor device or to a lead frame. In the semiconductor device, the bonding pads are respectively connected to lead frames by means of the bonding wires.
    Type: Grant
    Filed: October 24, 1984
    Date of Patent: July 7, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideharu Egawa, Katsuya Okumura
  • Patent number: 4547790
    Abstract: A semiconductor device includes p- and n-type semiconductor layers formed on an insulating substrate and gate electrodes selectively and insulatively formed over the respective p- and n-type semiconductor layers and forming D-type MOS transistors. In this semiconductor device, the p- and n-type semiconductor layers are made in contact with each other, and negative and positive power supply terminals which are respectively set at negative and positive potentials are respectively connected to the p- and n-type semiconductor layers thereby to electrically isolate the p-type and n-type semiconductor layers from each other.
    Type: Grant
    Filed: August 6, 1984
    Date of Patent: October 15, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Hideharu Egawa
  • Patent number: 4547681
    Abstract: A semiconductor device includes p- and n-type semiconductor layers formed on an insulating substrate and gate electrodes selectively and insulatively formed over the respective p- and n-type semiconductor layers and forming D-type MOS transistors. In this semiconductor device, the p- and n-type semiconductor layers are made in contact with each other, and negative and positive power supply terminals which are respectively set at negative and positive potentials are respectively connected to the p- and n-type semiconductor layers thereby to electrically isolate the p-type and n-type semiconductor layers from each other.
    Type: Grant
    Filed: June 26, 1984
    Date of Patent: October 15, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Hideharu Egawa
  • Patent number: 4491856
    Abstract: A semiconductor device includes p- and n-type semiconductor layers formed on an insulating substrate and an n-type interconnection layer formed to be electrically coupled with said n-type semiconductor layer. The n-type interconnection layer is formed in contact with the p-type semiconductor layer and is set at such a potential as to apply a reverse voltage across the p-n junction between the n-type interconnection layer and p-type semiconductor layer, so as to electrically isolate the n-type interconnection layer from the p-type semiconductor layer.
    Type: Grant
    Filed: February 27, 1984
    Date of Patent: January 1, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Hideharu Egawa, Yoshio Nishi, Kenji Maeguchi
  • Patent number: 4488674
    Abstract: The invention provides a bonding wire which prevents electric short-circuiting even if it comes into contact with another bonding wire, a bonding method using the same, and a semiconductor device including the same. The bonding wire comprises a core wire made of a metal and an insulating film which surrounds it. The insulating film is eliminated from the ends of the bonding wire by thermal decomposition and scattering, while simultaneously each end of the bonding wire is connected to a bonding pad of the semiconductor device or to a lead frame. In the semiconductor device, the bonding pads are respectively connected to lead frames by means of the bonding wires.
    Type: Grant
    Filed: September 24, 1982
    Date of Patent: December 18, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Hideharu Egawa, Katsuya Okumura
  • Patent number: 4280272
    Abstract: A complementary semiconductor device includes P-and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. N-and P-channel type silicon gate field effect transistors are formed in the P-and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.
    Type: Grant
    Filed: October 17, 1979
    Date of Patent: July 28, 1981
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Hideharu Egawa, Koji Matsuki, Yasoji Suzuki
  • Patent number: 4209830
    Abstract: A position and direction sensing mark is formed on an integrated circuit pellet formed with a prescribed electrode pattern. The position and direction sensing mark comprises a plurality of strips which are extended in a direction different from that in which the electrode pattern is extended and are arranged in turn at prescribed intervals in a direction intersecting the different direction at right angles thereto.
    Type: Grant
    Filed: August 9, 1978
    Date of Patent: June 24, 1980
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Yoshiaki Arimura, Hideharu Egawa, Yasoji Suzuki
  • Patent number: 4209797
    Abstract: A complementary semiconductor device includes P- and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. The N- and P-channel type silicon gate field effect transistors are formed in the P- and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.
    Type: Grant
    Filed: July 5, 1978
    Date of Patent: June 24, 1980
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Hideharu Egawa, Koji Matsuki, Yasoji Suzuki