Patents by Inventor Hidehiko Fujisaki

Hidehiko Fujisaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10396020
    Abstract: A board includes a plate-shaped member having a first wiring pattern, a first resin layer formed on a first surface of the plate-shaped member, the first surface having the first wiring pattern, a second resin layer stacked on the first resin layer, and a component fixed to the second resin layer in which a second wiring pattern formed on a second surface of the component is buried.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: August 27, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Kei Fukui, Youichi Hoshikawa, Hiromitsu Kobayashi, Hidehiko Fujisaki, Seigo Yamawaki, Masateru Koide, Manabu Watanabe, Daisuke Mizutani, Tomoyuki Akahoshi
  • Publication number: 20180315687
    Abstract: A board includes a plate-shaped member having a first wiring pattern, a first resin layer formed on a first surface of the plate-shaped member, the first surface having the first wiring pattern, a second resin layer stacked on the first resin layer, and a component fixed to the second resin layer in which a second wiring pattern formed on a second surface of the component is buried.
    Type: Application
    Filed: April 19, 2018
    Publication date: November 1, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Kei FUKUI, Youichi Hoshikawa, Hiromitsu KOBAYASHI, Hidehiko Fujisaki, Seigo Yamawaki, Masateru Koide, MANABU WATANABE, Daisuke Mizutani, Tomoyuki AKAHOSHI
  • Publication number: 20160338193
    Abstract: A multilayer board disclosed herein includes: a plurality of insulating layers made of a thermosetting resin and stacked on one another, each insulating layer being provided with a via hole; a plurality of wiring each formed between the insulating layers and including an inclined side surface; and a conductive via made of a cured product of conductive paste filled in the via hole and connecting the vertically adjacent wiring to each other. Here, orientations of the inclined side surfaces are alternately changed from the wiring to the wiring.
    Type: Application
    Filed: April 15, 2016
    Publication date: November 17, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Junichi Kanai, Yasuhiro Karahashi, Hirofumi Kobayashi, Shunsuke KOGOI, Junichi Murayama, Koji Komemura, Hidehiko Fujisaki
  • Patent number: 9345138
    Abstract: A method of manufacturing a laminated substrate, the method includes: forming a first diameter hole to a first surface of a first substrate so as not to penetrate the first substrate; forming a second diameter hole to a second surface of the first substrate so as to communicate with the first diameter hole; plating the first substrate to block the second diameter hole without blocking the first diameter hole; and laminating a second substrate on the second surface of the first substrate.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: May 17, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Takumi Hasegawa, Hidehiko Fujisaki
  • Publication number: 20150156874
    Abstract: A method of manufacturing a laminated substrate, the method includes: forming a first diameter hole to a first surface of a first substrate so as not to penetrate the first substrate; forming a second diameter hole to a second surface of the first substrate so as to communicate with the first diameter hole; plating the first substrate to block the second diameter hole without blocking the first diameter hole; and laminating a second substrate on the second surface of the first substrate.
    Type: Application
    Filed: August 27, 2014
    Publication date: June 4, 2015
    Inventors: Takumi HASEGAWA, Hidehiko FUJISAKI
  • Patent number: 7144687
    Abstract: A step of forming an insulating resin layer 31 includes a process of forming the insulating resin layer 31 made of a photo-sensitive resin on a load beam or a flexure 11 and an exposing and developing process in which a photo-mask 32 having different light transmittance between a part corresponding to a part near a slider mounting part 22 and other parts is applied to the insulating resin layer 31, exposed and developed so that the thickness of the insulating resin layer 31 of the part near the slider mounting part 22 is smaller than the thickness of the insulating resin layer 31 of other parts.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: December 5, 2006
    Assignee: TDK Corporation
    Inventors: Hidehiko Fujisaki, Kinnosuke Satou, Osamu Takahashi
  • Publication number: 20050037139
    Abstract: A step of forming an insulating resin layer 31 includes a process of forming the insulating resin layer 31 made of a photo-sensitive resin on a load beam or a flexure 11 and an exposing and developing process in which a photo-mask 32 having different light transmittance between a part corresponding to a part near a slider mounting part 22 and other parts is applied to the insulating resin layer 31, exposed and developed so that the thickness of the insulating resin layer 31 of the part near the slider mounting part 22 is smaller than the thickness of the insulating resin layer 31 of other parts.
    Type: Application
    Filed: July 1, 2004
    Publication date: February 17, 2005
    Applicant: TDK CORPORATION
    Inventors: Hidehiko Fujisaki, Kinnosuke Satou, Osamu Takahashi
  • Patent number: 6106688
    Abstract: Provided are a method for manufacturing a suspension element having a pattern of wiring lines and an equipment for the same. The method includes the steps of: preparing a roll of band-shaped sheet used as a substrate of the suspension element; sequentially performing processes to the sheet through a series of processing sections to integrally form the suspension element with the pattern of wiring lines within a predetermined region of the sheet, and transferring the sheet in a wound state like a roll from one of the processing sections to the next processing section.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: August 22, 2000
    Assignee: Fujitsu Limited
    Inventors: Yukio Miyazaki, Hitoshi Suzuki, Hidehiko Fujisaki, Koji Nakamura, Mitsuo Yamashita, Masami Nakajyoh, Masashi Takada