Abstract: In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.

Abstract: In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.

Abstract: In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.

Abstract: In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.

Abstract: In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.

Abstract: A computer and a backup computer exchange periodic report signal transmissions by way of SVP115. When there is no periodic report signal transmission from the main computer, the backup computer makes a main computer status inquiry and if one location is malfunctioning resets the main computer by way of the SVP115 and continues the processing. When permanent damage is present, the SVP115 continually resets the main computer and controls MOS switches of the common disk unit to isolate the SCSI from the main computer and continue the main computer processing.

Abstract: A compact and small compensating-electric-power data processor is realized by dividing a plurality of calculations to be carried out by a complex instruction into a number of executing units to be processed, instead of executing the calculations in parallel as in the past. For this purpose there is provided a decoder having a detecting part for decoding an instruction and for detecting whether the instruction is an instruction for executing a plurality of calculations, a field rearranging part for rearranging a part of the fields of said instruction based on a predetermined number of calculations to be processed if it is judged by said detecting part that the instruction is an instruction for executing a plurality of calculations, and a calculation control part for performing control to execute the calculations in plural cycles in synchronism with the order of said rearranged fields.

Abstract: In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.

Abstract: In a device and system which perform processing, (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.

Abstract: An arithmetic unit which accepts two numerical values and executes an operation by the use of the two numerical values; has an adder-subtracter for executing an addition or a subtraction on the basis of two numerical values obtained directly or indirectly from the accepted two numerical values; a normalizer for executing a normalizing process in which a mantissa part of an added or subtracted result is shifted so that a high-order digit having been developed anew in the result may come to a predetermined position, and in which an exponent part of the result is corrected in accordance with the number of shift places in the shift of the mantissa part; and a rounding device for executing a rounding process in which, on condition that the mantissa part of the added or subtracted result exceeds a predetermined number of digits, the number of digits of the mantissa part is reduced in conformity with a rounding mode designated beforehand.

Abstract: An arithmetic unit which accepts two numerical values and executes an operation by the use of the two numerical values has an adder-subtracter for executing an addition or a subtraction on the basis of two numerical values obtained directly or indirectly from the accepted two numerical values; a normalizer for executing a normalizing process in which a mantissa part of an added or subtracted result is shifted so that a high-order digit having been developed anew in the result may come to a predetermined position, and in which an exponent part of the result is corrected in accordance with the number of shift places in the shift of the mantissa part; and a rounding device for executing a rounding process in which, on condition that the mantissa part of the added or subtracted result exceeds a predetermined number of digits, the number of digits of the mantissa part is reduced in conformity with a rounding mode designated beforehand.